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參數(shù)資料
| 型號： | PIC24FJ64GB110T-I/PT |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 3/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PIC MCU FLASH 100TQFP |
| 標準包裝： | 1,200 |
| 系列： | PIC® 24F |
| 核心處理器： | PIC |
| 芯體尺寸： | 16-位 |
| 速度： | 32MHz |
| 連通性： | I²C，SPI，UART/USART，USB OTG |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，LVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 83 |
| 程序存儲器容量： | 64KB（22K x 24） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 16K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-TQFP |
| 包裝： | 帶卷 (TR) |
| 配用： | DM240011-ND - KIT STARTER MPLAB FOR PIC24F MCU MA240014-ND - MODULE PLUG-IN PIC24 |
| 其它名稱： | PIC24FJ64GB110T-I/PTTR |
2008-2011 Microchip Technology Inc.
DS80369N-page 11
PIC24FJ256GB110 FAMILY
32. Module: A/D Converter
Once
the
A/D
module
is
enabled
(AD1CON1<15> = 1), it may continue to draw
extra current, even if the module is later disabled
(AD1CON1<15> = 0).
Work around
In addition to disabling the module through the
ADON bit, set the corresponding PMD bit
(ADC1MD,
PMD1<0>)
to
power
it
down
completely.
Disabling the A/D module through the PMD regis-
ter also disables the AD1PCFG registers, which in
turn affects the state of any port pins with analog
inputs. Users should consider the effect on I/O
ports and other digital peripherals on those ports
when ADC1MD is used for power conservation.
Affected Silicon Revisions
33. Module: Oscillator
The POSCEN bit (OSCCON<2>) has no effect
when a Primary Oscillator with PLL mode is
selected (COSC<2:0> = 011). If XTPLL, HSPLL
or ECPLL Oscillator mode are selected, and the
device enters Sleep mode, the Primary Oscilla-
tor will be disabled, regardless of the state of the
POSCEN bit.
XT, HS and EC Oscillator modes (without the
PLL) will continue to operate as expected.
Work around
None.
Affected Silicon Revisions
34. Module: Output Compare (Interrupt)
Under certain circumstances, an Output Com-
pare match may cause the interrupt flag (OCxIF)
to become set prior to the Change-of-State
(COS) of the OCx pin. This has been observed
when all of the following are true:
the
module
is
in
One-Shot
mode
(OCM<2:0> = 001, 010 or 100);
one of the timer modules is being used as
the time base; and
a timer prescaler other than 1:1 is selected.
If the module is re-initialized by clearing
OCM<2:0> after the One-Shot compare, the
OCx pin may not be driven as expected.
Work around
After OCxIF is set, allow an interval (in CPU
cycles) of at least twice the prescaler factor to
elapse before clearing OCM<2:0>. For example,
for a prescaler value of 1:8, allow 16 CPU cycles
to elapse after the interrupt.
Affected Silicon Revisions
35. Module: CTMU
Using the CTMUMD bit (PMD4<2>) to selec-
tively power down the module may reduce the
accuracy of the internal band gap reference
(VBG). In those cases where VBG is used as a
reference for other analog modules, the accu-
racy of measurements or comparisons may be
affected.
Work around
If the A/D Converter or Comparators are being
used with VBG selected as a reference, do not set
the CTMUMD bit.
Affected Silicon Revisions
A3
A5
A6
XX
X
A3
A5
A6
XX
X
A3
A5
A6
XX
X
A3
A5
A6
XX
X
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