參數(shù)資料
型號: PIC24FJ48GA002-I/SS
廠商: Microchip Technology
文件頁數(shù): 42/52頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 48K 28-SSOP
產(chǎn)品培訓模塊: Graphics LCD System and PIC24 Interface
Asynchronous Stimulus
特色產(chǎn)品: PIC24FJ/33FJ MCUs & dsPIC? DSCs
標準包裝: 47
系列: PIC® 24F
核心處理器: PIC
芯體尺寸: 16-位
速度: 32MHz
連通性: I²C,PMP,SPI,UART/USART
外圍設備: 欠壓檢測/復位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 21
程序存儲器容量: 48KB(16K x 24)
程序存儲器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 647 (CN2011-ZH PDF)
配用: DM240011-ND - KIT STARTER MPLAB FOR PIC24F MCU
AC162088-ND - HEADER MPLAB ICD2 24FJ64GA004 28
AC164338-ND - MOD SKT PIC24F/DSPIC33F 28SOIC
DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
2008 Microchip Technology Inc.
DS39768D-page 47
PIC24FJXXXGA0XX
6.2
Checksum Computation
Checksums for the PIC24FJXXXGA0XX family are
16 bits in size. The checksum is calculated by summing
the following:
Contents of code memory locations
Contents of Configuration registers
Table 6-4 describes how to calculate the checksum for
each device. All memory locations are summed, one
byte at a time, using only their native data size. More
specifically, Configuration registers are summed by
adding the lower two bytes of these locations (the
upper byte is ignored), while code memory is summed
by adding all three bytes of code memory.
TABLE 6-4:
CHECKSUM COMPUTATION
Device
Read Code
Protection
Checksum Computation
Erased
Checksum
Value
Checksum with
0xAAAAAA at 0x0 and Last
Code Address
PIC24FJ16GA002
Disabled
CFGB + SUM(0:02BFB)
0xBB5A
0xB95C
Enabled
0
0x0000
PIC24FJ16GA004
Disabled
CFGB + SUM(0:02BFB)
0xBB5A
0xB95C
Enabled
0
0x0000
PIC24FJ32GA002
Disabled
CFGB + SUM(0:057FB)
0x795A
0x775C
Enabled
0
0x0000
PIC24FJ32GA004
Disabled
CFGB + SUM(0:057FB)
0x795A
0x775C
Enabled
0
0x0000
PIC24FJ48GA002
Disabled
CFGB + SUM(0:083FB)
0x375A
0x355C
Enabled
0
0x0000
PIC24FJ48GA004
Disabled
CFGB + SUM(0:083FB)
0x375A
0x355C
Enabled
0
0x0000
PIC24FJ64GA002
Disabled
CFGB + SUM(0:0ABFB)
0xFB5A
0xF95C
Enabled
0
0x0000
PIC24FJ64GA004
Disabled
CFGB + SUM(0:0ABFB)
0xFB5A
0xF95C
Enabled
0
0x0000
PIC24FJ64GA006
Disabled
CFGB + SUM(0:0ABFB)
0xFACC
0xF8CE
Enabled
0
0x0000
PIC24FJ64GA008
Disabled
CFGB + SUM(0:0ABFB)
0xFACC
0xF8CE
Enabled
0
0x0000
PIC24FJ64GA010
Disabled
CFGB + SUM(0:0ABFB)
0xFACC
0xF8CE
Enabled
0
0x0000
PIC24FJ96GA006
Disabled
CFGB + SUM(0:0FFFB)
0x7CCC
0x7ACE
Enabled
0
0x0000
PIC24FJ96GA008
Disabled
CFGB + SUM(0:0FFFB)
0x7CCC
0x7ACE
Enabled
0
0x0000
PIC24FJ96GA010
Disabled
CFGB + SUM(0:0FFFB)
0x7CCC
0x7ACE
Enabled
0
0x0000
Legend:
Item
Description
SUM[a:b]
=
Byte sum of locations, a to b inclusive (all 3 bytes of code memory)
CFGB
=
Configuration Block (masked),
64/80/100-Pin Devices = Byte sum of (CW1 & 0x7DDF + CW2 & 0x87E3)
28/44-Pin Devices = Byte sum of (CW1 & 0x7FDF + CW2 & 0xFFF7)
Note:
CW1 address is last location of implemented program memory; CW2 is (last location – 2).
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