參數(shù)資料
型號: PIC24FJ256GA106-E/MR
廠商: Microchip Technology
文件頁數(shù): 16/18頁
文件大小: 0K
描述: IC PIC MCU FLASH 256K 64-QFN
標準包裝: 40
系列: PIC® 24F
核心處理器: PIC
芯體尺寸: 16-位
速度: 32MHz
連通性: I²C,PMP,SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 53
程序存儲器容量: 256KB(85.5K x 24)
程序存儲器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 16x10b
振蕩器型: 內部
工作溫度: -40°C ~ 125°C
封裝/外殼: 64-VFQFN 裸露焊盤
包裝: 管件
2008-2011 Microchip Technology Inc.
DS80368L-page 7
PIC24FJ256GA110 FAMILY
14. Module: Core (Instruction Set)
If an instruction producing a read-after-write stall
condition is executed inside a REPEAT loop, the
instruction will be executed fewer times than was
intended. For example, this loop:
repeat #0xf
inc [w1],[++w1]
will execute less than 15 times.
Work around
Avoid using REPEAT to repetitively execute
instructions that create a stall condition. Instead,
use a software loop using conditional branches.
The MPLAB C Compiler will not generate
REPEAT
loops that cause this erratum.
Affected Silicon Revisions
15. Module: Memory (Program Space
Visibility)
When accessing data in the PSV area of data
RAM, it is possible to generate a false address
error trap condition by reading data located pre-
cisely at the lower address boundary (8000h). If
data is read using an instruction with an
auto-decrement, the resulting RAM address will be
below the PSV boundary (i.e., at 7FFEh); this will
result in an address error trap.
This false address error can also occur if a 32-bit
MOV
instruction is used to read the data at location
8000h.
Work around
Do not use the first location of a PSV page (address
8000h). The MPLAB C Compiler (v3.11 or later)
supports the option “-merrata=psv_trap” to
prevent it from generating code that would cause this
erratum.
Affected Silicon Revisions
16. Module: ICSP
The
ICSP/ICD
port
pair,
PGEC3/PGED3
(RB5/RB4), cannot be used to read or program the
device.
Work around
Use either PGEC2/PGED2 or PGEC1/PGED1.
Affected Silicon Revisions
17. Module: RTCC
Under certain circumstances, the value of the Alarm
Repeat Counter register (ALCFGRPT<7:0>) may
be unexpectedly decremented. This happens only
when a byte write to the upper byte of ALCFGRPT
is performed in the interval between a device
POR/BOR and the first edge from the RTCC clock
source.
Work around
Do not perform byte writes on ALCFGRPT,
particularly the upper byte.
Alternatively, wait until one period of the SOSC
has completed before performing byte writes to
ALCFGRPT.
Affected Silicon Revisions
A3
A5
A6
XX
X
A3
A5
A6
X
A3
A5
A6
X
A3
A5
A6
X
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