參數(shù)資料
    

    


    


    
型號(hào)：
PIC18LF14K50-I/MQ

    

    
廠(chǎng)商：
Microchip Technology

    

    
文件頁(yè)數(shù)：
229/285頁(yè)

    

    
文件大?。?/td>
0K

    

    
描述：
IC PIC MCU FLASH 768KX16 20-QFN

    

    
產(chǎn)品培訓(xùn)模塊：
XLP Deep Sleep Mode
    
	8-bit PIC® Microcontroller Portfolio
    		

    

    
標(biāo)準(zhǔn)包裝：
73

    

    
系列：
PIC® XLP™ 18F

    

    
核心處理器：
PIC
    		

    

    
芯體尺寸：
8-位
    		

    

    
速度：
48MHz
    		

    

    
連通性：
I²C，SPI，UART/USART，USB
    		

    

    
外圍設(shè)備：
欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
    		

    

    
輸入/輸出數(shù)：
14
    		

    

    
程序存儲(chǔ)器容量：
16KB（8K x 16）
    		

    

    
程序存儲(chǔ)器類(lèi)型：
閃存
    		

    

    
EEPROM 大?。?/td>
256 x 8
    		

    

    
RAM 容量：
768 x 8
    		

    

    
電壓 - 電源 (Vcc/Vdd)：
1.8 V ~ 3.6 V
    		

    

    
數(shù)據(jù)轉(zhuǎn)換器：
A/D 11x10b
    		

    

    
振蕩器型：
內(nèi)部
    		

    

    
工作溫度：
-40°C ~ 85°C
    		

    

    
封裝/外殼：
20-VQFN 裸露焊盤(pán)
    		

    

    
包裝：
管件
    		

    

    
產(chǎn)品目錄頁(yè)面：
656 (CN2011-ZH PDF)
    		

    

    

    

	
    
    
    
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    PIC18F1XK50/PIC18LF1XK50
    DS41350E-page 48
    Preliminary
     2010 Microchip Technology Inc.
    Operations on the FSRs with POSTDEC, POSTINC
    and PREINC affect the entire register pair; that is, roll-
    overs of the FSRnL register from FFh to 00h carry over
    to the FSRnH register. On the other hand, results of
    these operations do not change the value of any flags
    in the STATUS register (e.g., Z, N, OV, etc.).
    The PLUSW register can be used to implement a form
    of indexed addressing in the data memory space. By
    manipulating the value in the W register, users can
    reach addresses that are fixed offsets from pointer
    addresses. In some applications, this can be used to
    implement some powerful program control structure,
    such as software stacks, inside of data memory.
    3.4.3.3
    Operations by FSRs on FSRs
    Indirect addressing operations that target other FSRs
    or virtual registers represent special cases. For
    example, using an FSR to point to one of the virtual
    registers will not result in successful operations. As a
    specific case, assume that FSR0H:FSR0L contains
    FE7h, the address of INDF1. Attempts to read the
    value of the INDF1 using INDF0 as an operand will
    return 00h. Attempts to write to INDF1 using INDF0 as
    the operand will result in a NOP.
    On the other hand, using the virtual registers to write to
    an FSR pair may not occur as planned. In these cases,
    the value will be written to the FSR pair but without any
    incrementing or decrementing. Thus, writing to either
    the INDF2 or POSTDEC2 register will write the same
    value to the FSR2H:FSR2L.
    Since the FSRs are physical registers mapped in the
    SFR space, they can be manipulated through all direct
    operations. Users should proceed cautiously when
    working on these registers, particularly if their code
    uses indirect addressing.
    Similarly, operations by indirect addressing are generally
    permitted on all other SFRs. Users should exercise the
    appropriate caution that they do not inadvertently change
    settings that might affect the operation of the device.
    3.5
    Data Memory and the Extended
    Instruction Set
    Enabling the PIC18 extended instruction set (XINST
    Configuration bit = 1) significantly changes certain
    aspects of data memory and its addressing. Specifi-
    cally, the use of the Access Bank for many of the core
    PIC18 instructions is different; this is due to the intro-
    duction of a new addressing mode for the data memory
    space.
    What does not change is just as important. The size of
    the data memory space is unchanged, as well as its
    linear addressing. The SFR map remains the same.
    Core PIC18 instructions can still operate in both Direct
    and Indirect Addressing mode; inherent and literal
    instructions do not change at all. Indirect addressing
    with FSR0 and FSR1 also remain unchanged.
    3.5.1
    INDEXED ADDRESSING WITH
    LITERAL OFFSET
    Enabling the PIC18 extended instruction set changes
    the behavior of indirect addressing using the FSR2
    register pair within Access RAM. Under the proper
    conditions, instructions that use the Access Bank – that
    is, most bit-oriented and byte-oriented instructions –
    can invoke a form of indexed addressing using an
    offset
    specified
    in
    the
    instruction.
    This
    special
    addressing mode is known as Indexed Addressing with
    Literal Offset, or Indexed Literal Offset mode.
    When
    using
    the
    extended
    instruction
    set,
    this
    addressing mode requires the following:
     The use of the Access Bank is forced (‘a(chǎn)’ = 0) and
     The file address argument is less than or equal to
    5Fh.
    Under these conditions, the file address of the
    instruction is not interpreted as the lower byte of an
    address (used with the BSR in direct addressing), or as
    an 8-bit address in the Access Bank. Instead, the value
    is interpreted as an offset value to an Address Pointer,
    specified by FSR2. The offset and the contents of
    FSR2 are added to obtain the target address of the
    operation.
    3.5.2
    INSTRUCTIONS AFFECTED BY
    INDEXED LITERAL OFFSET MODE
    Any of the core PIC18 instructions that can use direct
    addressing are potentially affected by the Indexed
    Literal Offset Addressing mode. This includes all
    byte-oriented and bit-oriented instructions, or almost
    one-half of the standard PIC18 instruction set.
    Instructions that only use Inherent or Literal Addressing
    modes are unaffected.
    Additionally, byte-oriented and bit-oriented instructions
    are not affected if they do not use the Access Bank
    (Access RAM bit is ‘1’), or include a file address of 60h
    or above. Instructions meeting these criteria will
    continue to execute as before. A comparison of the
    different
    possible
    addressing
    modes
    when
    the
    extended instruction set is enabled is shown in
    Those who desire to use byte-oriented or bit-oriented
    instructions in the Indexed Literal Offset mode should
    note the changes to assembler syntax for this mode.
    This is described in more detail in Section 25.2.1
    
    
    
    
    
    


    


    

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    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
PIC18LF14K50T-I/MQ
 制造商:Microchip Technology Inc 功能描述:16 KB FLASH, 768 RAM, 15 I/O, 10-BIT ADC, USB 2.0, NANOWATT - Tape and Reel

    

    
PIC18LF14K50T-I/SO
功能描述:8位微控制器 -MCU 16 KB Flash768 RAM 15 I/O 10-Bit ADC
 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT

    

    
PIC18LF14K50T-I/SS
功能描述:8位微控制器 -MCU 16 KB Flash768 RAM 15 I/O 10-Bit ADC
 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT

    

    
PIC18LF2220-I/SO
功能描述:8位微控制器 -MCU 4KB 512 RAM 25I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT

    

    
PIC18LF2220-I/SP
功能描述:8位微控制器 -MCU 4KB 512 RAM 25I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT

    

    
    
    
    
	
    	
    
    
     
     
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