PIC18F2585/2680/4585/4680
DS39625C-page 170
Preliminary
2007 Microchip Technology Inc.
The ECCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
When the ECCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP1 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation.
EQUATION 15-3:
TABLE 15-4:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
15.4.3
PWM AUTO-SHUTDOWN
(ECCP1 ONLY)
The PWM auto-shutdown features of the Enhanced
CCP1
module
are
available
to
ECCP1
in
PIC18F4585/4680 (40/44-pin) devices. The operation
Auto-shutdown features are not available for CCP1.
15.4.4
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP1 module for PWM operation:
1.
Set the PWM period by writing to the PR2
register.
2.
Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
3.
Make the CCP1 pin an output by clearing the
appropriate TRIS bit.
4.
Set the TMR2 prescale value, then enable
Timer2 by writing to T2CON.
5.
Configure the CCP1 module for PWM operation.
Note:
If the PWM duty cycle value is longer than
the PWM period, the ECCP1 pin will not
be cleared.
PWM Resolution (max) =
FOSC
FPWM
log
log(2)
bits
PWM Frequency
2.44 kHz
9.77 kHz
39.06 kHz
156.25 kHz
312.50 kHz
416.67 kHz
Timer Prescaler (1, 4, 16)
16
41111
PR2 Value
FFh
3Fh
1Fh
17h
Maximum Resolution (bits)
14
12
10
8
7
6.58