參數資料
型號： PIC18F87K90-I/PTRSL
廠商： Microchip Technology
文件頁數： 15/110頁
文件大?。?/td> 0K
描述： MCU PIC 128K FLASH XLP 80TQFP
產品培訓模塊： 8-bit PIC® Microcontroller Portfolio
標準包裝： 119
系列： PIC® XLP™ 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 64MHz
連通性： I²C，LIN，SPI，UART/USART
外圍設備： 欠壓檢測/復位，LCD，POR，PWM，WDT
輸入/輸出數： 69
程序存儲器容量： 128KB（64K x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量： 4K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
數據轉換器： A/D 24x12b
振蕩器型： 內部
工作溫度： -40°C ~ 85°C
封裝/外殼： 80-TQFP
包裝： 托盤
PIC18F47J53 FAMILY
DS39964B-page 462
Preliminary
2010 Microchip Technology Inc.
TABLE 29-2:
PIC18F47J53 FAMILY INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
16-Bit Instruction Word
Status
Affected
Notes
MSb
LSb
BYTE-ORIENTED OPERATIONS
ADDWF
ADDWFC
ANDWF
CLRF
COMF
CPFSEQ
CPFSGT
CPFSLT
DECF
DECFSZ
DCFSNZ
INCF
INCFSZ
INFSNZ
IORWF
MOVF
MOVFF
MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
SUBFWB
SUBWF
SUBWFB
SWAPF
TSTFSZ
XORWF
f, d, a
f, a
f, d, a
f, a
f, d, a
fs, fd
f, a
f, d, a
f, a
f, d, a
f, a
f, d, a
Add WREG and f
Add WREG and Carry bit to f
AND WREG with f
Clear f
Complement f
Compare f with WREG, Skip =
Compare f with WREG, Skip >
Compare f with WREG, Skip <
Decrement f
Decrement f, Skip if 0
Decrement f, Skip if Not 0
Increment f
Increment f, Skip if 0
Increment f, Skip if Not 0
Inclusive OR WREG with f
Move f
Move fs (source) to 1st word
fd (destination) 2nd word
Move WREG to f
Multiply WREG with f
Negate f
Rotate Left f through Carry
Rotate Left f (No Carry)
Rotate Right f through Carry
Rotate Right f (No Carry)
Set f
Subtract f from WREG with
Borrow
Subtract WREG from f
Subtract WREG from f with
Borrow
Swap Nibbles in f
Test f, Skip if 0
Exclusive OR WREG with f
1
1 (2 or 3)
1
1 (2 or 3)
1
1 (2 or 3)
1
2
1
1 (2 or 3)
1
0010
0001
0110
0001
0110
0000
0010
0100
0010
0011
0100
0001
0101
1100
1111
0110
0000
0110
0011
0100
0011
0100
0110
0101
0011
0110
0001
01da
00da
01da
101a
11da
001a
010a
000a
01da
11da
10da
11da
10da
00da
ffff
111a
001a
110a
01da
00da
100a
01da
11da
10da
011a
10da
ffff
C, DC, Z, OV, N
Z, N
Z
Z, N
None
C, DC, Z, OV, N
None
C, DC, Z, OV, N
None
Z, N
None
C, DC, Z, OV, N
C, Z, N
Z, N
C, Z, N
Z, N
None
C, DC, Z, OV, N
None
Z, N
1, 2
1,2
2
1, 2
4
1, 2
1, 2, 3, 4
1, 2
1, 2, 3, 4
4
1, 2
1
1, 2
4
1, 2
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared
if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
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