參數(shù)資料
型號(hào): PIC18F87J72-I/PT
廠(chǎng)商: Microchip Technology
文件頁(yè)數(shù): 15/24頁(yè)
文件大?。?/td> 0K
描述: IC PIC MCU 8BIT 14KB FLSH 80TQFP
產(chǎn)品培訓(xùn)模塊: 8-bit PIC® Microcontroller Portfolio
特色產(chǎn)品: PIC18F87J72 High-Performance Microcontrollers
標(biāo)準(zhǔn)包裝: 119
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 48MHz
連通性: I²C,LIN,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LCD,LVD,POR,PWM,WDT
輸入/輸出數(shù): 51
程序存儲(chǔ)器容量: 128KB(64K x 16)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 3.8K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 80-TQFP
包裝: 管件
配用: ARD00330-ND - DAUGHTER BOARD PIC18F87J72
ADM00333-ND - BOARD EVAL FOR PIC18F87J72
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P89LPC915_916_917_5
NXP
B
.V
.2009.
All
r
ights
reser
v
ed.
Pr
oduct
data
sheet
Re
v
.05
15
December
2009
22
of
75
NXP
Semiconductor
s
P89LPC915/916/917
8-bit
micr
ocontr
oller
s
with
accelerated
tw
o-c
loc
k
80C51
core
[1]
All ports are in input only (high-impedance) state after power-up.
[2]
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
[3]
The RSTSRC register reects the cause of the P89LPC915/916/917 reset. Upon a power-up reset, all reset source ags are cleared except POF and BOF; the power-on reset
value is xx11 0000.
[4]
After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.
Other resets will not affect WDTOF.
[5]
On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
[6]
The only reset source that affects these SFRs is power-on reset.
Bit address
8F
8E
8D
8C
8B
8A
89
88
TCON*
Timer 0 and 1 control
88H
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00
0000 0000
TH0
Timer 0 high
8CH
00
0000 0000
TH1
Timer 1 high
8DH
00
0000 0000
TL0
Timer 0 low
8AH
00
0000 0000
TL1
Timer 1 low
8BH
00
0000 0000
TMOD
Timer 0 and 1 mode
89H
T1GATE
T1C/T
T1M1
T1M0
T0GATE
T0C/T
T0M1
T0M0
00
0000 0000
TRIM
Internal oscillator trim register
96H
RCCLK
-
TRIM.5
TRIM.4
TRIM.3
TRIM.2
TRIM.1
TRIM.0
WDCON
Watchdog control register
A7H
PRE2
PRE1
PRE0
-
WDRUN
WDTOF
WDCLK
WDL
Watchdog load
C1H
FF
1111 1111
WFEED1
Watchdog feed 1
C2H
WFEED2
Watchdog feed 2
C3H
Table 7.
P89LPC915 special function registers …continued
* indicates SFRs that are bit addressable.
Name
Description
SFR
addr.
Bit functions and addresses
Reset value
MSB
LSB
Hex
Binary
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