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參數資料
| 型號： | PIC18F2682-I/SO |
| 廠商： | Microchip Technology |
| 文件頁數： | 61/183頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PIC MCU FLASH 40KX16 28SOIC |
| 產品培訓模塊： | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 標準包裝： | 27 |
| 系列： | PIC® 18F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | CAN，I²C，SPI，UART/USART |
| 外圍設備： | 欠壓檢測/復位，HLVD，POR，PWM，WDT |
| 輸入/輸出數： | 25 |
| 程序存儲器容量： | 80KB（40K x 16） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 1K x 8 |
| RAM 容量： | 3.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.2 V ~ 5.5 V |
| 數據轉換器： | A/D 8x10b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 包裝： | 管件 |
| 產品目錄頁面： | 646 (CN2011-ZH PDF) |
| 配用： | XLT28SO-1-ND - SOCKET TRANSITION 28SOIC 300MIL |
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2011 Microchip Technology Inc.
DS39931D-page 153
PIC18F46J50 FAMILY
10.7.3.3
Mapping Limitations
The control schema of the PPS is extremely flexible.
Other than systematic blocks that prevent signal con-
tention caused by two physical pins being configured
as the same functional input, or two functional outputs
configured as the same pin, there are no hardware
enforced lock outs. The flexibility extends to the point of
allowing a single input to drive multiple peripherals or a
single functional output to drive multiple output pins.
10.7.4
CONTROLLING CONFIGURATION
CHANGES
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. PIC18F devices include three features to
prevent alterations to the peripheral map:
Control register lock sequence
Continuous state monitoring
Configuration bit remapping lock
10.7.4.1
Control Register Lock
Under normal operation, writes to the RPINRx and
RPORx registers are not allowed. Attempted writes will
appear to execute normally, but the contents of the
registers will remain unchanged. To change these reg-
isters, they must be unlocked in hardware. The register
lock is controlled by the IOLOCK bit (PPSCON<0>).
Setting IOLOCK prevents writes to the control
registers; clearing IOLOCK allows writes.
To set or clear IOLOCK, a specific command sequence
must be executed:
1.
Write 55h to EECON2<7:0>.
2.
Write AAh to EECON2<7:0>.
3.
Clear (or set) IOLOCK as a single operation.
IOLOCK remains in one state until changed. This
allows all of the PPS registers to be configured with a
single unlock sequence, followed by an update to all
control registers, then locked with a second lock
sequence.
10.7.4.2
Continuous State Monitoring
In addition to being protected from direct writes, the
contents of the RPINRx and RPORx registers are
constantly monitored in hardware by shadow registers.
If an unexpected change in any of the registers occurs
(such as cell disturbances caused by ESD or other
external events), a Configuration Mismatch Reset will
be triggered.
10.7.4.3
Configuration Bit Pin Select Lock
As an additional level of safety, the device can be
configured to prevent more than one write session to
the RPINRx and RPORx registers. The IOL1WAY
(CONFIG3H<0>) Configuration bit blocks the IOLOCK
bit from being cleared after it has been set once. If
IOLOCK remains set, the register unlock procedure will
not execute and the PPS Control registers cannot be
written to. The only way to clear the bit and re-enable
peripheral remapping is to perform a device Reset.
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to one write session. Programming
IOL1WAY allows users unlimited access (with the
proper use of the unlock sequence) to the PPS
registers.
10.7.5
CONSIDERATIONS FOR
PERIPHERAL PIN SELECTION
The ability to control Peripheral Pin Selection intro-
duces several considerations into application design
that could be overlooked. This is particularly true for
several common peripherals that are available only as
remappable peripherals.
The main consideration is that the PPS is not available
on default pins in the device’s default (Reset) state.
Since all RPINRx registers reset to ‘11111’ and all
RPORx registers reset to ‘00000’, all PPS inputs are
tied to RP31 and all PPS outputs are disconnected.
This situation requires the user to initialize the device
with the proper peripheral configuration before any
other application code is executed. Since the IOLOCK
bit resets in the unlocked state, it is not necessary to
execute the unlock sequence after the device has
come out of Reset.
For application safety, however, it is best to set
IOLOCK and lock the configuration after writing to the
control registers.
The unlock sequence is timing-critical. Therefore, it is
recommended that the unlock sequence be executed
as an assembly language routine with interrupts
temporarily disabled. If the bulk of the application is
written in ‘C’ or another high-level language, the unlock
sequence should be performed by writing in-line
assembly.
Note:
In tying PPS inputs to RP31, RP31 does
not have to exist on a device for the
registers to be reset to it.
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| PIC18F2682T-I/SO | 功能描述:8位微控制器 -MCU 80KB 3328bytes-RAM 25I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| PIC18F2685-E/SO | 功能描述:8位微控制器 -MCU 96KB 3328bytes-RAM 25I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| PIC18F2685-E/SP | 功能描述:8位微控制器 -MCU 96KB 3328bytes-RAM 25I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| PIC18F2685-I/SO | 功能描述:8位微控制器 -MCU 96KB 3328bytes-RAM 25I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| PIC18F2685-I/SO | 制造商:Microchip Technology Inc 功能描述:8-Bit Microcontroller IC |
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