參數(shù)資料
型號： PIC18F2520-I/SP
廠商： Microchip Technology
文件頁數(shù)： 22/151頁
文件大小： 0K
描述： IC MCU FLASH 16KX16 28-DIP
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝： 15
系列： PIC® 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 40MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，HLVD，POR，PWM，WDT
輸入/輸出數(shù)： 25
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量： 1.5K x 8
電壓 - 電源 (Vcc/Vdd)： 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-DIP（0.300"，7.62mm）
包裝： 管件
產(chǎn)品目錄頁面： 643 (CN2011-ZH PDF)
配用： MCP3909RD-3PH1-ND - REF DESIGN MCP3909 3PH ENGY MTR
DVA18XP280-ND - DEVICE ADAPTER 18F2220 PDIP 28LD
PIC16(L)F1782/3
DS41579C-page 290
Preliminary
2011-2012 Microchip Technology Inc.
26.5.4
SLAVE MODE 10-BIT ADDRESS
RECEPTION
This section describes a standard sequence of events
for the MSSP module configured as an I2C slave in
10-bit Addressing mode.
Figure 26-19 is used as a visual reference for this
description.
This is a step by step process of what must be done by
slave software to accomplish I2C communication.
1.
Bus starts Idle.
2.
Master sends Start condition; S bit of SSPSTAT
is set; SSPIF is set if interrupt on Start detect is
enabled.
3.
Master sends matching high address with R/W
bit clear; UA bit of the SSPSTAT register is set.
4.
Slave sends ACK and SSPIF is set.
5.
Software clears the SSPIF bit.
6.
Software reads received address from SSPBUF
clearing the BF flag.
7.
Slave loads low address into SSPADD,
releasing SCL.
8.
Master sends matching low address byte to the
slave; UA bit is set.
9.
Slave sends ACK and SSPIF is set.
10. Slave clears SSPIF.
11. Slave reads the received matching address
from SSPBUF clearing BF.
12. Slave loads high address into SSPADD.
13. Master clocks a data byte to the slave and
clocks out the slaves ACK on the 9th SCL pulse;
SSPIF is set.
14. If SEN bit of SSPCON2 is set, CKP is cleared by
hardware and the clock is stretched.
15. Slave clears SSPIF.
16. Slave reads the received byte from SSPBUF
clearing BF.
17. If SEN is set the slave sets CKP to release the
SCL.
18. Steps 13-17 repeat for each received byte.
19. Master sends Stop to end the transmission.
26.5.5
10-BIT ADDRESSING WITH ADDRESS OR
DATA HOLD
Reception using 10-bit addressing with AHEN or
DHEN set is the same as with 7-bit modes. The only
difference is the need to update the SSPADD register
using the UA bit. All functionality, specifically when the
CKP bit is cleared and SCL line is held low are the
same. Figure 26-20 can be used as a reference of a
slave in 10-bit addressing with AHEN set.
Figure 26-21 shows a standard waveform for a slave
transmitter in 10-bit Addressing mode.
Note:
Updates to the SSPADD register are not
allowed until after the ACK sequence.
Note:
If the low address does not match, SSPIF
and UA are still set so that the slave soft-
ware can set SSPADD back to the high
address. BF is not set because there is no
match. CKP is unaffected.
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