參數(shù)資料
型號(hào): PIC17LC766T-08/PT
廠商: Microchip Technology
文件頁(yè)數(shù): 79/159頁(yè)
文件大小: 0K
描述: IC MCU OTP 16KX16 A/D PWM 80TQFP
標(biāo)準(zhǔn)包裝: 1,200
系列: PIC® 17C
核心處理器: PIC
芯體尺寸: 8-位
速度: 8MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 66
程序存儲(chǔ)器容量: 32KB(16K x 16)
程序存儲(chǔ)器類型: OTP
RAM 容量: 902 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 80-TQFP
包裝: 帶卷 (TR)
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2000 Microchip Technology Inc.
DS30289B-page 25
PIC17C7XX
5.1.4
TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows: First,
the internal POR signal goes high when the POR trip
point is reached. If MCLR is high, then both the OST and
PWRT timers start. In general, the PWRT time-out is
longer, except with low frequency crystals/resonators.
The total time-out also varies based on oscillator config-
uration. Table 5-1 shows the times that are associated
with the oscillator configuration. Figure 5-5 and Figure 5-
6 display these time-out sequences.
If the device voltage is not within electrical specification
at the end of a time-out, the MCLR/VPP pin must be
held low until the voltage is within the device specifica-
tion. The use of an external RC delay is sufficient for
many of these applications.
The time-out sequence begins from the first rising edge
of MCLR.
Table 5-3 shows the RESET conditions for some spe-
cial registers, while Table 5-4 shows the initialization
conditions for all the registers.
TABLE 5-1:
TIME-OUT IN VARIOUS SITUATIONS
TABLE 5-2:
STATUS BITS AND THEIR SIGNIFICANCE
TABLE 5-3:
RESET CONDITION FOR THE PROGRAM COUNTER AND THE CPUSTA REGISTER
Oscillator
Configuration
POR, BOR
Wake-up from
SLEEP
MCLR Reset
XT, LF
Greater of: 96 ms or 1024TOSC
1024TOSC
EC, RC
Greater of: 96 ms or 1024TOSC
——
POR
BOR(1)
TO
PD
Event
00
1
Power-on Reset
11
1
0
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
11
0
1
WDT Reset during normal operation
11
0
WDT Wake-up during SLEEP
11
1
MCLR Reset during normal operation
10
1
Brown-out Reset
00
0
x
Illegal, TO is set on POR
00
x
0
Illegal, PD is set on POR
xx
1
CLRWDT
instruction executed
Note 1: When BODEN is enabled, else the BOR status bit is unknown.
Event
PCH:PCL
CPUSTA(4)
OST Active
Power-on Reset
0000h
--11 1100
Yes
Brown-out Reset
0000h
--11 1110
Yes
MCLR Reset during normal operation
0000h
--11 1111
No
MCLR Reset during SLEEP
0000h
--11 1011
Yes(2)
WDT Reset during normal operation
0000h
--11 0111
No
WDT Reset during SLEEP(3)
0000h
--11 0011
Yes(2)
Interrupt Wake-up from SLEEP
GLINTD is set
PC + 1
--11 1011
Yes(2)
GLINTD is clear
PC + 1(1)
--10 1011
Yes(2)
Legend: u = unchanged, x = unknown, - = unimplemented, read as '0'
Note 1: On wake-up, this instruction is executed. The instruction at the appropriate interrupt vector is fetched and
then executed.
2: The OST is only active (on wake-up) when the oscillator is configured for XT or LF modes.
3: The Program Counter = 0; that is, the device branches to the RESET vector and places SFRs in WDT
Reset states. This is different from the mid-range devices.
4: When BODEN is enabled, else the BOR status bit is unknown.
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