參數(shù)資料
型號(hào): PIC16LF818T-I/SS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 10 MHz, RISC MICROCONTROLLER, PDSO20
封裝: 0.209 INCH, PLASTIC, MO-150, SSOP-20
文件頁數(shù): 57/176頁
文件大小: 3124K
代理商: PIC16LF818T-I/SS
2004 Microchip Technology Inc.
DS39598E-page 13
PIC16F818/819
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details on
page:
Bank 0
00h(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
01h
TMR0
Timer0 Module Register
xxxx xxxx
02h(1)
PCL
Program Counter’s (PC) Least Significant Byte
0000 0000
03h(1)
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
04h(1)
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
05h
PORTA
PORTA Data Latch when written; PORTA pins when read
xxx0 0000
06h
PORTB
PORTB Data Latch when written; PORTB pins when read
xxxx xxxx
07h
Unimplemented
08h
Unimplemented
09h
Unimplemented
0Ah(1,2)
PCLATH
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
0Bh(1)
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
0Ch
PIR1
—ADIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
-0-- 0000
0Dh
PIR2
EEIF
---0 ----
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
10h
T1CON
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
--00 0000
11h
TMR2
Timer2 Module Register
0000 0000
12h
T2CON
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
-000 0000
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx
14h
SSPCON
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
15h
CCPR1L
Capture/Compare/PWM Register (LSB)
xxxx xxxx
16h
CCPR1H
Capture/Compare/PWM Register (MSB)
xxxx xxxx
17h
CCP1CON
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000
18h
Unimplemented
19h
Unimplemented
1Ah
Unimplemented
1Bh
Unimplemented
1Ch
Unimplemented
1Dh
Unimplemented
1Eh
ADRESH
A/D Result Register High Byte
xxxx xxxx
1Fh
ADCON0
ADCS1
ADCS0
CHS2
CHS1
CHS0
GO/DONE
—ADON
0000 00-0
Legend:
x
= unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1:
These registers can be addressed from any bank.
2:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are
transferred to the upper byte of the program counter.
3:
Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
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