ADDRESSING I2C DEVICES" />
    參數(shù)資料
    型號: PIC16LC76-04I/SP
    廠商: Microchip Technology
    文件頁數(shù): 105/114頁
    文件大小: 0K
    描述: IC MCU OTP 8KX14 A/D PWM 28DIP
    產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
    8-bit PIC® Microcontroller Portfolio
    標(biāo)準(zhǔn)包裝: 15
    系列: PIC® 16C
    核心處理器: PIC
    芯體尺寸: 8-位
    速度: 4MHz
    連通性: I²C,SPI,UART/USART
    外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
    輸入/輸出數(shù): 22
    程序存儲器容量: 14KB(8K x 14)
    程序存儲器類型: OTP
    RAM 容量: 368 x 8
    電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 6 V
    數(shù)據(jù)轉(zhuǎn)換器: A/D 5x8b
    振蕩器型: 外部
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 28-DIP(0.300",7.62mm)
    包裝: 管件
    PIC16C7X
    DS30390E-page 90
    1997 Microchip Technology Inc.
    11.4.2
    ADDRESSING I2C DEVICES
    There are two address formats. The simplest is the
    7-bit address format with a R/W bit (Figure 11-15). The
    more complex is the 10-bit address with a R/W bit
    (Figure 11-16). For 10-bit address format, two bytes
    must be transmitted with the rst ve bits specifying this
    to be a 10-bit address.
    FIGURE 11-15: 7-BIT ADDRESS FORMAT
    FIGURE 11-16: I2C 10-BIT ADDRESS FORMAT
    11.4.3
    TRANSFER ACKNOWLEDGE
    All data must be transmitted per byte, with no limit to the
    number of bytes transmitted per data transfer. After
    each byte, the slave-receiver generates an acknowl-
    edge bit (ACK) (Figure 11-17). When a slave-receiver
    doesn’t acknowledge the slave address or received
    data, the master must abort the transfer. The slave
    must leave SDA high so that the master can generate
    the STOP condition (Figure 11-14).
    S
    R/W ACK
    Sent by
    Slave
    slave address
    S
    R/W
    Read/Write pulse
    MSb
    LSb
    Start Condition
    ACK
    Acknowledge
    S 1 1 1 1 0 A9 A8 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK
    sent by slave
    = 0 for write
    S
    R/W
    ACK
    - Start Condition
    - Read/Write Pulse
    - Acknowledge
    FIGURE 11-17: SLAVE-RECEIVER
    ACKNOWLEDGE
    If the master is receiving the data (master-receiver), it
    generates an acknowledge signal for each received
    byte of data, except for the last byte. To signal the end
    of data to the slave-transmitter, the master does not
    generate an acknowledge (not acknowledge). The
    slave then releases the SDA line so the master can
    generate the STOP condition. The master can also
    generate the STOP condition during the acknowledge
    pulse for valid termination of data transfer.
    If the slave needs to delay the transmission of the next
    byte, holding the SCL line low will force the master into
    a wait state. Data transfer continues when the slave
    releases the SCL line. This allows the slave to move the
    received data or fetch the data it needs to transfer
    before allowing the clock to start. This wait state tech-
    nique can also be implemented at the bit level,
    Figure 11-18. The slave will inherently stretch the clock,
    when it is a transmitter, but will not when it is a receiver.
    The slave will have to clear the SSPCON<4> bit to
    enable clock stretching when it is a receiver.
    S
    Data
    Output by
    Transmitter
    Data
    Output by
    Receiver
    SCL from
    Master
    Start
    Condition
    Clock Pulse for
    Acknowledgment
    not acknowledge
    acknowledge
    1
    2
    8
    9
    FIGURE 11-18: DATA TRANSFER WAIT STATE
    12
    7
    8
    9
    1
    2
    3
    89
    P
    SDA
    SCL
    S
    Start
    Condition
    Address
    R/W
    ACK
    Wait
    State
    Data
    ACK
    MSB
    acknowledgment
    signal from receiver
    acknowledgment
    signal from receiver
    byte complete
    interrupt with receiver
    clock line held low while
    interrupts are serviced
    Stop
    Condition
    Applicable Devices
    72 73 73A 74 74A 76 77
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