310
8018P–AVR–08/10
ATmega169P
Notes:
1.
tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits
commands.
2.
tWLRH_CE is valid for the Chip Erase command.
27.8
Serial Downloading
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while
RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-
put). After RESET is set low, the Programming Enable instruction needs to be executed first
mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal
SPI interface.
tDVXH
Data and Control Valid before XTAL1 High
67
ns
tXLXH
XTAL1 Low to XTAL1 High
200
tXHXL
XTAL1 Pulse Width High
150
tXLDX
Data and Control Hold after XTAL1 Low
67
tXLWL
XTAL1 Low to WR Low
0
tXLPH
XTAL1 Low to PAGEL high
0
tPLXH
PAGEL low to XTAL1 high
150
tBVPH
BS1 Valid before PAGEL High
67
tPHPL
PAGEL Pulse Width High
150
tPLBX
BS1 Hold after PAGEL Low
67
tWLBX
BS2/1 Hold after WR Low
67
tPLWL
PAGEL Low to WR Low
67
tBVWL
BS1 Valid to WR Low
67
tWLWH
WR Pulse Width Low
150
tWLRL
WR Low to RDY/BSY Low
0
1
μs
tWLRH
3.7
4.5
ms
tWLRH_CE
WR Low to RDY/BSY High for Chip Erase
7.5
9
tXLOL
XTAL1 Low to OE Low
0
ns
tBVDV
BS1 Valid to DATA valid
0
250
tOLDV
OE Low to DATA Valid
250
tOHDZ
OE High to DATA Tri-stated
250
Table 27-13. Parallel Programming Characteristics, V
CC = 5V ±10%
Symbol
Parameter
Min
Typ
Max
Units