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    參數(shù)資料
    型號: PIC16F871T-E/L
    廠商: Microchip Technology
    文件頁數(shù): 66/143頁
    文件大?。?/td> 0K
    描述: IC MCU CMOS 20MHZ 2K FLSH 44PLCC
    標(biāo)準(zhǔn)包裝: 500
    系列: PIC® 16F
    核心處理器: PIC
    芯體尺寸: 8-位
    速度: 20MHz
    連通性: UART/USART
    外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
    輸入/輸出數(shù): 33
    程序存儲器容量: 3.5KB(2K x 14)
    程序存儲器類型: 閃存
    EEPROM 大小: 64 x 8
    RAM 容量: 128 x 8
    電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
    數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
    振蕩器型: 外部
    工作溫度: -40°C ~ 125°C
    封裝/外殼: 44-LCC(J 形引線)
    包裝: 帶卷 (TR)
    2003 Microchip Technology Inc.
    DS30569B-page 27
    PIC16F870/871
    3.0
    DATA EEPROM AND FLASH
    PROGRAM MEMORY
    The Data EEPROM and FLASH Program Memory are
    readable and writable during normal operation over the
    entire VDD range. A bulk erase operation may not be
    issued from user code (which includes removing code
    protection). The data memory is not directly mapped in
    the register file space. Instead, it is indirectly addressed
    through the Special Function Registers (SFR).
    There are six SFRs used to read and write the program
    and data EEPROM memory. These registers are:
    EECON1
    EECON2
    EEDATA
    EEDATH
    EEADR
    EEADRH
    The EEPROM data memory allows byte read and write.
    When interfacing to the data memory block, EEDATA
    holds the 8-bit data for read/write and EEADR holds the
    address of the EEPROM location being accessed. The
    registers EEDATH and EEADRH are not used for data
    EEPROM access. The PIC16F870/871 devices have
    64 bytes of data EEPROM with an address range from
    0h to 3Fh.
    The EEPROM data memory is rated for high erase/
    write cycles. The write time is controlled by an on-chip
    timer. The write time will vary with voltage and temper-
    ature, as well as from chip-to-chip. Please refer to the
    specifications for exact limits.
    The program memory allows word reads and writes.
    Program memory access allows for checksum calcula-
    tion and calibration table storage. A byte or word write
    automatically erases the location and writes the new
    data (erase before write). Writing to program memory
    will cease operation until the write is complete. The pro-
    gram memory cannot be accessed during the write,
    therefore code cannot execute. During the write opera-
    tion, the oscillator continues to clock the peripherals,
    and therefore, they continue to operate. Interrupt
    events will be detected and essentially “queued” until
    the write is completed. When the write completes, the
    next instruction in the pipeline is executed and the
    branch to the interrupt vector address will occur.
    When interfacing to the program memory block, the
    EEDATH:EEDATA registers form a two-byte word,
    which holds the 14-bit data for read/write. The
    EEADRH:EEADR registers form a two-byte word,
    which holds the 13-bit address of the FLASH location
    being accessed. The PIC16F870/871 devices have
    2K words of program FLASH with an address range
    from 0h to 7FFh. The unused upper bits in both the
    EEDATH and EEDATA registers all read as ‘0’s.
    The value written to program memory does not need to
    be a valid instruction. Therefore, up to 14-bit numbers
    can be stored in memory for use as calibration param-
    eters, serial numbers, packed 7-bit ASCII, etc. Execut-
    ing a program memory location containing data that
    forms an invalid instruction results in a NOP.
    3.1
    EEADR
    The address registers can address up to a maximum of
    256 bytes of data EEPROM or up to a maximum of
    8K words
    of
    program
    FLASH.
    However,
    the
    PIC16F870/871 have 64 bytes of data EEPROM and
    2K words of program FLASH.
    When selecting a program address value, the MSByte
    of the address is written to the EEADRH register and
    the LSByte is written to the EEADR register. When
    selecting a data address value, only the LSByte of the
    address is written to the EEADR register.
    On the PIC16F870/871 devices, the upper two bits of
    the EEADR must always be cleared to prevent inad-
    vertent access to the wrong location in data EEPROM.
    This also applies to the program memory. The upper
    five MSbits of EEADRH must always be clear during
    program FLASH access.
    3.2
    EECON1 and EECON2 Registers
    The EECON1 register is the control register for config-
    uring and initiating the access. The EECON2 register is
    not a physically implemented register, but is used
    exclusively in the memory write sequence to prevent
    inadvertent writes.
    There are many bits used to control the read and write
    operations to EEPROM data and FLASH program
    memory. The EEPGD bit determines if the access will
    be a program or data memory access. When clear, any
    subsequent operations will work on the EEPROM data
    memory. When set, all subsequent operations will
    operate in the program memory.
    Read operations only use one additional bit, RD, which
    initiates the read operation from the desired memory
    location. Once this bit is set, the value of the desired
    memory location will be available in the data registers.
    This bit cannot be cleared by firmware. It is automati-
    cally cleared at the end of the read operation. For
    EEPROM data memory reads, the data will be avail-
    able in the EEDATA register in the very next instruction
    cycle after the RD bit is set. For program memory
    reads,
    the
    data
    will
    be
    loaded
    into
    the
    EEDATH:EEDATA registers, following the second
    instruction after the RD bit is set.
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