參數(shù)資料
型號: PIC16F72-I/SO
廠商: Microchip Technology
文件頁數(shù): 70/136頁
文件大小: 0K
描述: IC PIC MCU FLASH 2KX14 28-SOIC
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 27
系列: PIC® 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 22
程序存儲器容量: 3.5KB(2K x 14)
程序存儲器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 5x8b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 639 (CN2011-ZH PDF)
配用: XLT28SO-1-ND - SOCKET TRANSITION 28SOIC 300MIL
2007 Microchip Technology Inc.
DS39597C-page 37
PIC16F72
8.0
CAPTURE/COMPARE/PWM
(CCP) MODULE
The CCP (Capture/Compare/PWM) module contains a
16-bit register that can operate as a:
16-bit capture register
16-bit compare register
PWM master/slave duty cycle register.
Table 8-1 shows the timer resources of the CCP
Module modes.
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
Additional information on the CCP module is available
in the PIC Mid-Range MCU Reference Manual,
(DS33023).
TABLE 8-1:
CCP MODE - TIMER
RESOURCE
REGISTER 8-1:
CCPCON1: CAPTURE/COMPARE/PWM CONTROL REGISTER 1 (ADDRESS 17h)
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1
Timer2
U-0
R/W-0
CCPxX
CCPxY
CCPxM3
CCPxM2
CCPxM1
CCPxM0
bit 7
bit 0
bit 7-6
Unimplemented: Read as '0'
bit 5-4
CCPxX:CCPxY: PWM Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0
CCPxM3:CCPxM0: CCPx Mode Select bits
0000
= Capture/Compare/PWM disabled (resets CCPx module)
0100
= Capture mode, every falling edge
0101
= Capture mode, every rising edge
0110
= Capture mode, every 4th rising edge
0111
= Capture mode, every 16th rising edge
1000
= Compare mode, set output on match (CCPxIF bit is set)
1001
= Compare mode, clear output on match (CCPxIF bit is set)
1010
= Compare mode, generate software interrupt on match (CCPxIF bit is set,
CCPx pin is unaffected)
1011
= Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected);
CCP1 resets TMR1 and starts an A/D conversion (if A/D module is enabled)
11xx
= PWM mode
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
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