參數(shù)資料
型號(hào)： PIC16F630-I/ML
廠商： Microchip Technology
文件頁(yè)數(shù)： 82/132頁(yè)
文件大?。?/td> 0K
描述： IC PIC MCU FLASH 1KX14 16QFN
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝： 91
系列： PIC® 16F
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，WDT
輸入/輸出數(shù)： 12
程序存儲(chǔ)器容量： 1.75KB（1K x 14）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 128 x 8
RAM 容量： 64 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 16-VQFN 裸露焊盤
包裝： 管件
產(chǎn)品目錄頁(yè)面： 638 (CN2011-ZH PDF)
配用： AC164324-ND - MODULE SKT FOR MPLAB 8DFN/16QFN
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2010 Microchip Technology Inc.
DS40039F-page 53
PIC16F630/676
8.3
READING THE EEPROM DATA
MEMORY
To read a data memory location, the user must write the
address to the EEADR register and then set control bit
RD (EECON1<0>), as shown in Example 8-1. The data
is available in the very next cycle in the EEDATA
register. Therefore, it can be read in the next
instruction. EEDATA holds this value until another read,
or until it is written to by the user (during a write
operation).
EXAMPLE 8-1:
DATA EEPROM READ
8.4
WRITING TO THE EEPROM DATA
MEMORY
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then the user must follow a
specific sequence to initiate the write for each byte, as
shown in Example 8-2.
EXAMPLE 8-2:
DATA EEPROM WRITE
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment. A cycle count is executed during the
required sequence. Any number that is not equal to the
required cycles to execute the required sequence will
prevent the data from being written into the EEPROM.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. The EEIF bit
(PIR<7>) register must be cleared by software.
8.5
WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the data
EEPROM should be verified (see Example 8-3) to the
desired value to be written.
EXAMPLE 8-3:
WRITE VERIFY
8.5.1
USING THE DATA EEPROM
The data EEPROM is a high-endurance, byte address-
able array that has been optimized for the storage of
frequently
changing
information
(e.g.,
program
variables or other data that are updated often).
Frequently changing values will typically be updated
more often than specifications D120 or D120A. If this is
not the case, an array refresh must be performed. For
this reason, variables that change infrequently (such as
constants, IDs, calibration, etc.) should be stored in
Flash program memory.
8.6
PROTECTION AGAINST
SPURIOUS WRITE
There are conditions when the user may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built in. On power-up, WREN is cleared. Also, the
Power-up
Timer
(72
ms
duration)
prevents
EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during:
brown-out
power glitch
software malfunction
BSF
STATUS,RP0
;Bank 1
MOVLW CONFIG_ADDR
;
MOVWF EEADR
;Address to read
BSF
EECON1,RD
;EE Read
MOVF
EEDATA,W
;Move data to W
BSF
STATUS,RP0
;Bank 1
BSF
EECON1,WREN
;Enable write
BCF
INTCON,GIE
;Disable INTs
MOVLW 55h
;Unlock write
MOVWF EECON2
;
MOVLW AAh
;
MOVWF EECON2
;
BSF
EECON1,WR
;Start the write
BSF
INTCON,GIE
;Enable INTS
Re
qu
ire
d
S
equ
en
ce
BCF
STATUS,RP0
;Bank 0
:
;Any code
BSF
STATUS,RP0
;Bank 1 READ
MOVF
EEDATA,W
;EEDATA not changed
;from previous write
BSF
EECON1,RD
;YES, Read the
;value written
XORWF EEDATA,W
BTFSS STATUS,Z
;Is data the same
GOTO
WRITE_ERR
;No, handle error
:
;Yes, continue
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參數(shù)描述
PIC16F630T-E/SL 功能描述:8位微控制器 -MCU 1.75KB 64 RAM 12 I/O Ext Temp SOIC14 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F630T-E/ST 功能描述:8位微控制器 -MCU 1.75KB 64 RAM 12 I/O Ext Temp TSSOP14 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F630T-I/ML 功能描述:8位微控制器 -MCU 1.75KB 64 RAM 12I/O Ind Temp QFN RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F630T-I/SL 功能描述:8位微控制器 -MCU 1.75KB 64 RAM 12 I/O Ind Temp SOIC14 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F630T-I/ST 功能描述:8位微控制器 -MCU 1.75KB 64 RAM 12 I/O Ind Temp TSSOP14 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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