參數(shù)資料
型號: PIC16F1827-I/P
廠商: Microchip Technology
文件頁數(shù): 84/109頁
文件大小: 0K
描述: IC PIC MCU FLASH 4K 18-DIP
產(chǎn)品培訓(xùn)模塊: 8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 25
系列: PIC® XLP™ mTouch™ 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 32MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 7KB(4K x 14)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 384 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 18-DIP(0.300",7.62mm)
包裝: 管件
產(chǎn)品目錄頁面: 655 (CN2011-ZH PDF)
SC16C850
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 11 November 2010
36 of 55
NXP Semiconductors
SC16C850
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
7.22 Advanced Feature Control Register 1 (AFCR1)
[1]
It takes 4 XTAL1 clocks to reset the device.
Table 32.
Advanced Feature Control Register 1 register bits description
Bit
Symbol
Description
7:5
AFCR1[7:5]
reserved
4
AFCR1[4]
Sleep RXLow. Program RX input to be edge-sensitive or level-sensitive.
logic 0 = RX input is level-sensitive. If RX pin is LOW, the UART will
not go to sleep. Once the UART is in Sleep mode, it will wake up if RX
pin goes LOW.
logic 1 = RX input is edge-sensitive. UART will go to sleep even if RX
pin is LOW, and will wake up when RX pin toggles.
3
AFCR1[3]
reserved
2
AFCR1[2]
RTS/CTS mapped to DTR/DSR. Switch the function of RTS/CTS to
DTR/DSR.
logic 0 = RTS and CTS signals are used for hardware flow control.
logic 1 = DTR and DSR signals are used for hardware flow control.
RTS and CTS retain their functionality.
1
AFCR1[1]
SReset. Software Reset. A write to this bit will reset the UART. Once the
UART is reset this bit is automatically set to 0.[1]
0
AFCR1[0]
TSR Interrupt. Select TSR interrupt mode
logic 0 = transmit empty interrupt occurs when transmit FIFO falls
below the trigger level or becomes empty.
logic 1 = transmit empty interrupt occurs when transmit FIFO falls
below the trigger level, or becomes empty and the last stop bit has
been shifted out of the Transmit Shift Register.
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