參數(shù)資料
型號: PIC16C72A-04/SP
廠商: Microchip Technology
文件頁數(shù): 68/120頁
文件大?。?/td> 0K
描述: IC MCU OTP 2KX14 A/D PWM 28DIP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 15
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 4MHz
連通性: I²C,SPI
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 22
程序存儲器容量: 3.5KB(2K x 14)
程序存儲器類型: OTP
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 5x8b
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 28-DIP(0.300",7.62mm)
包裝: 管件
PIC16C62B/72A
1999 Microchip Technology Inc.
Preliminary
DS35008B-page 51
When the A/D conversion is complete, the result is
loaded into the ADRES register, the GO/DONE bit,
ADCON0<2>, is cleared, and the A/D interrupt flag bit,
ADIF, is set. The block diagram of the A/D module is
shown in Figure 9-1.
The value that is in the ADRES register is not modified
for a Power-on Reset. The ADRES register will contain
unknown data after a Power-on Reset.
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 9.1.
After this acquisition time has elapsed, the A/D conver-
sion can be started. The following steps should be fol-
lowed for doing an A/D conversion:
1.
Configure the A/D module:
Configure analog pins / voltage reference /
and digital I/O (ADCON1)
Select A/D input channel (ADCON0)
Select A/D conversion clock (ADCON0)
Turn on A/D module (ADCON0)
2.
Configure A/D interrupt (if desired):
Clear ADIF bit
Set ADIE bit
Set GIE bit
3.
Wait the required acquisition time.
4.
Start conversion:
Set GO/DONE bit (ADCON0)
5.
Wait for A/D conversion to complete, by either:
Polling for the GO/DONE bit to be cleared
OR
Waiting for the A/D interrupt
6.
Read A/D Result register (ADRES), clear bit
ADIF if required.
7.
For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
FIGURE 9-1:
A/D BLOCK DIAGRAM
(Input voltage)
VIN
VREF
(Reference
voltage)
VDD
PCFG2:PCFG0
CHS2:CHS0
000 or
010 or
100 or
001 or
011 or
101
RA5/AN4
RA3/AN3/VREF
RA2/AN2
RA1/AN1
RA0/AN0
100
011
010
001
000
A/D
Converter
11x
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