參數(shù)資料
型號(hào): PIC16C433-I/SO
廠商: Microchip Technology
文件頁數(shù): 69/126頁
文件大小: 0K
描述: IC MCU CMOS 8BIT 10MHZ 2K 18SOIC
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 42
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 10MHz
連通性: LIN(本地互連網(wǎng)絡(luò))
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 5
程序存儲(chǔ)器容量: 3.5KB(2K x 14)
程序存儲(chǔ)器類型: OTP
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 18-SOIC(0.295",7.50mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 636 (CN2011-ZH PDF)
配用: XLT18SO-1-ND - SOCKET TRANSITION 18SOIC 300MIL
2002 Microchip Technology Inc.
Preliminary
DS41139B-page 45
PIC16C433
The ADRES Register contains the result of the A/D
conversion. When the A/D conversion is complete, the
result is loaded into the ADRES register, the GO/DONE
bit (ADCON0<2>) is cleared and A/D interrupt flag bit
ADIF (PIE1<6>) is set. The block diagrams of the A/D
module are shown in Figure 8-1.
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine sample time, see Section 8.1. After
this acquisition time has elapsed, the A/D conversion
can be started. The following steps should be followed
for doing an A/D conversion:
1.
Configure the A/D module:
Configure analog pins/voltage reference/ and
digital I/O (ADCON1 and TRIS)
Select A/D input channel (ADCON0)
Select A/D conversion clock (ADCON0)
Turn on A/D module (ADCON0)
2.
Configure A/D interrupt (if desired):
Clear ADIF bit
Set ADIE bit
Set GIE bit
3.
Wait the required acquisition time.
4.
Start conversion:
Set GO/DONE bit (ADCON0)
5.
Wait for A/D conversion to complete, by either:
Polling for the GO/DONE bit to be cleared
OR
Waiting for the A/D interrupt
6.
Read A/D Result Register (ADRES), clear bit
ADIF if required.
7.
For the next conversion, go to step 1, step 2, or
step 3, as required. The A/D conversion time per
bit is defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
FIGURE 8-1:
A/D BLOCK DIAGRAM
(Input Voltage)
V
IN
V
REF
(Reference
Voltage)
V
DD
PCFG<2:0>
CHS<1:0>
GP4/AN3
GP0/AN0
GP2/AN2
GP1/AN1/V
REF
11
10
01
00
A/D
Converter
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