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參數資料
| 型號： | PIC12F519-I/MS |
| 廠商： | Microchip Technology |
| 文件頁數： | 16/96頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PIC MCU FLASH 1KX12 8MSOP |
| 產品培訓模塊： | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 標準包裝： | 100 |
| 系列： | PIC® 12F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 8MHz |
| 外圍設備： | POR，WDT |
| 輸入/輸出數： | 5 |
| 程序存儲器容量： | 1.5KB（1K x 12） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 41 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 5.5 V |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 包裝： | 管件 |
| 產品目錄頁面： | 637 (CN2011-ZH PDF) |
| 配用： | AC162096-ND - HEADER MPLAB ICD2 PIC16F526 8/14 AC164325-ND - MODULE SKT FOR 8MSOP |
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2008 Microchip Technology Inc.
DS41319B-page 21
PIC12F519
5.0
FLASH DATA MEMORY
CONTROL
The Flash data memory is readable and writable during
normal operation (full VDD range). This memory is not
directly mapped in the register file space. Instead, it is
indirectly addressed through the Special Function
Registers (SFRs).
5.1
Reading Flash Data Memory
To read a Flash data memory location the user must:
Write the EEADR register
Set the RD bit of the EECON register
The value written to the EEADR register determines
which Flash data memory location is read. Setting the
RD bit of the EECON register initiates the read. Data
from the Flash data memory read is available in the
EEDATA register immediately. The EEDATA register
will hold this value until another read is initiated or it is
modified by a write operation. Program execution is
suspended while the read cycle is in progress. Execu-
tion will continue with the instruction following the one
that sets the WR bit. See Example 1 for sample code.
EXAMPLE 1:
READING FROM FLASH
DATA MEMORY
5.2
Writing and Erasing Flash Data
Memory
Flash data memory is erased one row at a time and
written one byte at a time. The 64-byte array is made
up of eight rows. A row contains eight sequential bytes.
Row boundaries exist every eight bytes.
Generally, the procedure to write a byte of data to Flash
data memory is:
1.
Identify the row containing the address where
the byte will be written.
2.
If there is other information in that row that must
be saved, copy those bytes from Flash data
memory to RAM.
3.
Perform a row erase of the row of interest.
4.
Write the new byte of data and any saved bytes
back to the appropriate addresses in Flash data
memory.
To prevent accidental corruption of the Flash Data
Memory, an unlock sequence is required to initiate a
write or erase cycle. This sequence requires that the bit
set instructions used to configure the EECON register
happen exactly as shown in Example 2 and Example 3,
depending on the operation requested.
5.2.1
ERASING FLASH DATA MEMORY
A row must be manually erased before writing new
data. The following sequence must be performed for a
single row erase.
1.
Load EEADR with an address in the row to be
erased.
2.
Set the FREE bit to enable the erase.
3.
Set the WREN bit to enable write access to the
array.
4.
Set the WR bit to initiate the erase cycle.
If the WREN bit is not set in the instruction cycle after
the FREE bit is set, the FREE bit will be cleared in
hardware.
If the WR bit is not set in the instruction cycle after the
WREN bit is set, the WREN bit will be cleared in
hardware.
Sample code that follows this procedure is included in
Program execution is suspended while the erase cycle
is in progress. Execution will continue with the instruc-
tion following the one that sets the WR bit.
EXAMPLE 2:
ERASING A FLASH DATA
MEMORY ROW
Note:
Only a BSF command will work to enable the
Flash data memory read documented in
Example 1. No other sequence of com-
mands will work, no exceptions.
BANKSEL EEADR
;
MOVF DATA_EE_ADDR, W
;
MOVWF EEADR
;Data Memory
;Address to read
BANKSEL EECON1
;
BSF EECON, RD
;EE Read
MOVF EEDATA, W
;W = EEDATA
Note 1:
The FREE bit may be set by any com-
mand normally used by the core. How-
ever, the WREN and WR bits can only be
set using a series of BSF commands, as
documented in Example 1. No other
sequence of commands will work, no
exceptions.
2:
Bits <5:3> of the EEADR register indicate
which row is to be erased.
BANKSEL
EEADR
MOVLW
EE_ADR_ERASE
; LOAD ADDRESS OF ROW TO
; ERASE
MOVWF
EEADR
;
BSF
EECON,FREE
; SELECT ERASE
BSF
EECON,WREN
; ENABLE WRITES
BSF
EECON,WR
; INITITATE ERASE
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相關代理商/技術參數 |
參數描述 |
|---|---|
| PIC12F519T-E/MC | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:8-Pin, 8-Bit Flash Microcontroller |
| PIC12F519T-E/MS | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:8-Pin, 8-Bit Flash Microcontroller |
| PIC12F519T-E/P | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:8-Pin, 8-Bit Flash Microcontroller |
| PIC12F519T-E/SN | 制造商:Microchip Technology Inc 功能描述:8-PIN, 1.5KB FLASH PROGRAM, 64 - Tape and Reel |
| PIC12F519T-I/MC | 功能描述:8位微控制器 -MCU 15KB Flash Prgrm 64B 8MHz Intrnl Oscilatr RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
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