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| 型號： | PIC12F1840-I/MF |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 93/122頁 |
| 文件大?。?/td> | 0K |
| 描述： | MCU 7KB FLASH 256B RAM 8-DFN |
| 產(chǎn)品培訓(xùn)模塊： | 8-bit PIC® Microcontroller Portfolio |
| 標(biāo)準(zhǔn)包裝： | 120 |
| 系列： | PIC® XLP™ 12F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 32MHz |
| 連通性： | I²C，LIN，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 5 |
| 程序存儲器容量： | 7KB（4K x 14） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大小： | 256 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.3 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 4x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-VDFN 裸露焊盤 |
| 包裝： | 管件 |
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PIC12(L)F1840
DS41441B-page 72
Preliminary
2011 Microchip Technology Inc.
7.3
MCLR
The MCLR is an optional external input that can reset
the device. The MCLR function is controlled by the
MCLRE bit of Configuration Word 1 and the LVP bit of
Configuration Word 2 (Table 7-2).
7.3.1
MCLR ENABLED
When MCLR is enabled and the pin is held low, the
device is held in Reset. The MCLR pin is connected to
VDD through an internal weak pull-up.
The device has a noise filter in the MCLR Reset path.
The filter will detect and ignore small pulses.
7.3.2
MCLR DISABLED
When MCLR is disabled, the pin functions as a general
purpose input and the internal weak pull-up is under
software control. See Section 12.2 “PORTA Registers”
for more information.
7.4
Watchdog Timer (WDT) Reset
The Watchdog Timer generates a Reset if the firmware
does not issue a CLRWDT instruction within the time-out
period. The TO and PD bits in the STATUS register are
changed to indicate the WDT Reset. See Section 10.0
for more information.
7.5
RESET
Instruction
A RESET instruction will cause a device Reset. The RI
bit in the PCON register will be set to ‘0’. See Table 7-4
for default conditions after a RESET instruction has
occurred.
7.6
Stack Overflow/Underflow Reset
The device can reset when the Stack Overflows or
Underflows. The STKOVF or STKUNF bits of the PCON
register indicate the Reset condition. These Resets are
enabled by setting the STVREN bit in Configuration
Word 2. See Section 3.4.2 “Overflow/Underflow
for more information.
7.7
Programming Mode Exit
Upon exit of Programming mode, the device will
behave as if a POR had just occurred.
7.8
Power-Up Timer
The Power-up Timer optionally delays device execution
after a BOR or POR event. This timer is typically used to
allow VDD to stabilize before allowing the device to start
running.
The Power-up Timer is controlled by the PWRTE bit of
Configuration Word 1.
7.9
Start-up Sequence
Upon the release of a POR or BOR, the following must
occur before the device will begin executing:
1.
Power-up Timer runs to completion (if enabled).
2.
Oscillator start-up timer runs to completion (if
required for oscillator source).
3.
MCLR must be released (if enabled).
The total time-out will vary based on oscillator configu-
ration and Power-up Timer configuration. See
for more information.
The Power-up Timer and oscillator start-up timer run
independently of MCLR Reset. If MCLR is kept low long
enough, the Power-up Timer and oscillator start-up
timer will expire. Upon bringing MCLR high, the device
will begin execution immediately (see Figure 7-4). This
is useful for testing purposes or to synchronize more
than one device operating in parallel.
TABLE 7-2:
MCLR CONFIGURATION
MCLRE
LVP
MCLR
00
Disabled
10
Enabled
x1
Enabled
Note:
A Reset does not drive the MCLR pin low.
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| PIC12F1840T-I/MF | 功能描述:8位微控制器 -MCU 7KB Flash EEPROM 256b nanoWatt RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC12F1840T-I/SN | 功能描述:8位微控制器 -MCU 7KB Flash EEPROM 256b nanoWatt RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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