參數(shù)資料
型號(hào)： PIC12C508-04/P
廠商： Microchip Technology
文件頁(yè)數(shù)： 29/113頁(yè)
文件大小： 0K
描述： IC MCU OTP 512X12 8DIP
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝： 60
系列： PIC® 12C
核心處理器： PIC
芯體尺寸： 8-位
速度： 4MHz
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 5
程序存儲(chǔ)器容量： 768B（512 x 12）
程序存儲(chǔ)器類(lèi)型： OTP
RAM 容量： 25 x 8
電壓 - 電源 (Vcc/Vdd)： 2.5 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： 0°C ~ 70°C
封裝/外殼： 8-DIP（0.300"，7.62mm）
包裝： 管件
配用： DVMCPA-ND - KIT DVR BOARD EVAL SYSTEM MXDEV1
DVA12XP080-ND - ADAPTER DEVICE FOR MPLAB-ICE
AC124001-ND - MODULE SKT PROMATEII 8DIP/SOIC
PIC12C5XX
DS40139E-page 22
1999 Microchip Technology Inc.
TABLE 5-1:
SUMMARY OF PORT REGISTERS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-On
Reset
Value on
All Other Resets
N/A
TRIS
—
--11 1111
N/A
OPTION
GPWU
GPPU
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
03H
STATUS
GPWUF
—
PAO
TO
PD
Z
DC
C
0001 1xxx
q00q quuu
(1)
06h
GPIO
(PIC12C508/
PIC12C509/
PIC12C508A/
PIC12C509A/
PIC12CR509A)
—
GP5
GP4
GP3
GP2
GP1
GP0
--xx xxxx
--uu uuuu
06h
GPIO
(PIC12CE518/
PIC12CE519)
SCL
SDA
GP5
GP4
GP3
GP2
GP1
GP0
11xx xxxx
11uu uuuu
Legend: Shaded cells not used by Port Registers, read as ‘0’, — = unimplemented, read as '0', x = unknown, u = unchanged,
q = see tables in Section 8.7 for possible values.
Note 1:
If reset was due to wake-up on change, then bit 7 = 1. All other resets will cause bit 7 = 0.
5.4
I/O Programming Considerations
5.4.1
BI-DIRECTIONAL I/O PORTS
Some instructions operate internally as read followed
by write operations. The BCF and BSF instructions, for
example, read the entire port into the CPU, execute
the bit operation and re-write the result. Caution must
be used when these instructions are applied to a port
where one or more pins are used as input/outputs. For
example, a BSF operation on bit5 of GPIO will cause
all eight bits of GPIO to be read into the CPU, bit5 to
be set and the GPIO value to be written to the output
latches. If another bit of GPIO is used as a bi-
directional I/O pin (say bit0) and it is defined as an
input at this time, the input signal present on the pin
itself would be read into the CPU and rewritten to the
data latch of this particular pin, overwriting the
previous content. As long as the pin stays in the input
mode, no problem occurs. However, if bit0 is switched
into output mode later on, the content of the data latch
may now be unknown.
Example 5-1 shows the effect of two sequential read-
modify-write instructions (e.g., BCF, BSF, etc.) on an
I/O port.
A pin actively outputting a high or a low should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-
and”). The resulting high output currents may damage
the chip.
EXAMPLE 5-1:
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
;Initial GPIO Settings
; GPIO<5:3> Inputs
; GPIO<2:0> Outputs
;
GPIO latch
GPIO pins
;
----------
BCF
GPIO, 5
;--01 -ppp
--11 pppp
BCF
GPIO, 4
;--10 -ppp
--11 pppp
MOVLW 007h
;
TRIS
GPIO
;--10 -ppp
--11 pppp
;
;Note that the user may have expected the pin
;values to be --00 pppp. The 2nd BCF caused
;GP5 to be latched as the pin value (High).
5.4.2
SUCCESSIVE OPERATIONS ON I/O
PORTS
The actual write to an I/O port happens at the end of
an instruction cycle, whereas for reading, the data
must be valid at the beginning of the instruction cycle
(Figure 5-2). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should
allow the pin voltage to stabilize (load dependent)
before the next instruction, which causes that file to be
read into the CPU, is executed. Otherwise, the
previous state of that pin may be read into the CPU
rather than the new state. When in doubt, it is better to
separate these instructions with a NOP or another
instruction not accessing this I/O port.
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