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參數資料
| 型號： | PI4S706PW |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封裝： | 0.150 INCH, PLASTIC, SOIC-8 |
| 文件頁數： | 4/8頁 |
| 文件大?。?/td> | 398K |
| 代理商： | PI4S706PW |
4
PS8703
09/23/03
PI4S705, PI4S706x, PI4S707, PI4S708x, PI4S813L
P Supervisor Circuts
Functional Description
The PI4S70xxx/813L family can assert reset output during power-up,
power-down and brownout conditions for uP system, detect power
failure or low-battery conditions with a 1.25V threshold detector and
have watchdog functions. Refer to Function Reference Table for their
individual features. For the typical application see Figure 4.
Reset Output
The supervisory circuits can assert reset for a microprocessor during
power-up, power-down and brownout to prevent code execution
errors.
On power-up, once VCC reaches about 1.2V, RESET is a guaranteed
logic low of 0.4V or less. As VCC rises, RESET stays low. When
VCC rises above the reset threshold, an internal timer releases
RESET after about 200ms. RESET pulses low whenever VCC
drops below the reset threshold (brownout condition). If brownout
occurs in the middle of a previously initiated reset pulse, the pulse
continues for at least another 140ms.
On power-down, once VCC falls below the reset threshold, RESET
stays low and is guaranteed to be 0.4V or less until Vcc drops
below 1.2V.
The PI4S706xH, PI4S707, PI4S708x and PI4S813L active-high
RESET output is simply the complement of the RESET output,
and is guaranteed to be valid with VCC down to 1.2V. Some Ps,
such as Intel’s 80C51, require an active-high reset pulse.
Watchdog Timer
The watchdog circuit monitors the P’s activity. If the P does not
toggle the watchdog input (WDI) within 1.6sec and WDI is not in
high impedance, WDO goes low. As long as RESET is asserted or
the WDI input is in high impedance, the watchdog timer will stay
cleared and will not count. As soon as reset is released and WDI
is driven high or low, the timer will start counting. Pulses as short
as 50ns can be detected.
Typically, WDO will be connected to the non-maskable interrupt
input (NMI) of a P. When VCC drops below the reset threshold,
WDO will go low whether or not the watchdog timer has timed
out yet. Normally this would trigger an NMI interrupt, but RESET
goes low simultaneously, and thus overrides the NMI interrupt. If
WDI is left unconnected, WDO can be used as a low-line output.
Since floating WDI disables the internal timer, WDO goes low
only when VCC falls below the reset threshold, thus functioning
as a low-line output.
Manual Reset
The manual-reset input (MR) allows reset to be triggered by a push-
button switch. The switch is effectively debounced by the 140ms
minimum reset pulse width. MR is TTL/CMOS logic compatible,
so it can be driven by any external logic line.
Power-Fail Comparator
The power-fail comparator will send out a low signal once detects
a voltage lowered than 1.25V. It can be used for various purposes
because its output and non-inverting input are not internally
connected. The inverting input is internally connected to a 1.25V
reference.
Typical Application Circuit
DC Linear
Regulator
Vcc
Supervisory
PFI
Circuit
WDI
P
Vcc
RESET
I/O Line
NMI
Interrupt
IN
OUT
RESET
WDO
PFO
MR
P
Unregulated DC
相關PDF資料 |
PDF描述 |
|---|---|
| PI4S706HW | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| PI4S706SHWE | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| PI4S708TW | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| PI4S708WE | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| PI4S706HWE | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
相關代理商/技術參數 |
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| PI4ULS3V08M | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:1.2V to 3.6V Universal Bi-directional Level Shifter with Automatic Direction Control & Advanced Package Solution |
| PI4ULS3V08MZLE | 功能描述:轉換 - 電壓電平 8bit Auto Direction Sensing Volt Trans RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
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