參數(shù)資料
型號: PI2EQX4402NBE
廠商: Pericom
文件頁數(shù): 2/7頁
文件大小: 0K
描述: IC PCI-EXPRESS REPEATER 84-LFBGA
產(chǎn)品變化通告: Product Discontinuation 03/Oct/2011
標準包裝: 260
類型: 轉(zhuǎn)發(fā)器
Tx/Rx類型: CML
電源電壓: 1.7 V ~ 1.9 V
安裝類型: 表面貼裝
封裝/外殼: 84-LFBGA
供應(yīng)商設(shè)備封裝: 84-LFBGA(9x9)
包裝: 管件
2
PS8778E
02/15/06
PI2EQX4402
2.5Gbps x2 Lane Serial PCI Express Repeater / Equalizer
Pin Description
Pin #
Pin Name
I/O
Description
B1, F1, D2, E2,
B3, F3, H4, B8,
F8, B10, F10
VDD
PWR
1.8V Supply Voltage
C3
AI+
I
Positive CML Input Channel A with internal 50 pull down
D3
AI-
I
Negative CML Input Channel A with internal 50 pull down
E1, J1, F2, E3, J3,
H7, E8, J8, D9,
E9, F9, E10, J10
GND
PWR
Supply Ground
C8
BI+
I
Positive CML Input Channel B with internal 50 pull down
D8
BI-
I
Negative CML Input Channel B with internal 50 pull down
G3
CI+
I
Positive CML Input Channel C with internal 50 pull down
H3
CI-
I
Negative CML Input Channel C with internal 50 pull down
G8
DI+
I
Positive CML Input Channel D with internal 50 pull down
H8
DI-
I
Negative CML Input Channel D with internal 50 pull down
A3, B4, B5
SEL[0:2]_A
I
Selection pins for equalizer (see Amplifier Configuration Table)
w/ 50K internal pull up
A4, C4, C5
SEL[0:2]_B
I
G2, J2, J4
SEL[0:2]_C
I
H2, K2, J5
SEL[0:2]_D
I
B6, A5
SEL[3:4]_A
I
Selection pins for amplifier (see Amplifier Configuration Table)
w/ 50K internal pull up
C6, A6
SEL[3:4]_B
I
K3, K4
SEL[3:4]_C
I
J6, J9
SEL[3:4]_D
I
B7, A7
SEL[5:6]_A
I
Selection pins for De-Emphasis (See De-Emphasis Configuration Table)
w/ 50K internal pull up
C7, A8
SEL[5:6]_B
I
K9, G9
SEL[5:6]_C
I
K10, H9
SEL[5:6]_D
I
C10
AO+
O
Positive CML Output Channel A internal 50 pull up during normal operation and
2K pull up otherwise.
D10
AO-
O
Negative CML Output Channel A with internal 50 pull up during normal opera-
tion and 2K pull up otherwise.
C1
BO+
O
Positive CML Output Channel B with internal 50 pull up during normal opera-
tion and 2K pull up otherwise.
D1
BO-
O
Negative CMLOutput Channel B with internal 50 pull up during normal opera-
tion and 2K pull up otherwise.
G10
CO+
O
Positive CMLOutput Channel C with internal 50 pull up during normal operation
and 2K pull up otherwise.
H10
CO-
O
Negative CMLOutput Channel C with internal 50 pull up during normal opera-
tion and 2K pull up otherwise.
G1
DO+
O
Positive CMLOutput Channel D with internal 50 pull up during normal operation
and 2K pull up otherwise.
H1
DO-
O
Negative CMLOutput Channel D with internal 50 pull up during normal opera-
tion and 2K pull up otherwise.
A9, A10, B9, C9
EN_
[A,B,C,D]
I
EN_[A:D] is the enable pin with internal 50K pull up resistor. A LVCMOS high
provides normal operation. A LVCMOS low selects a low power down mode.
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