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參數(shù)資料
| 型號： | PF38F1020WYTQ1 |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA88 |
| 封裝： | 8 X 10 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, SCSP-88 |
| 文件頁數(shù)： | 8/23頁 |
| 文件大?。?/td> | 364K |
| 代理商： | PF38F1020WYTQ1 |
32-Mbit W18 + 8-Mbit SRAM (38F1020W0YTQ1, 38F1020W0YBQ1)
28 Jun 2005
Intel StrataFlash Wireless Memory (W18 SCSP)
Datasheet
16
Order Number: 252635, Revision: 003
W8
tWR
Write Recovery
0
–
ns
4
W9
tBW
R-UB#, R-LB# Setup to R-WE# (S-CS1#) Going High
60
–
ns
Notes:
1.
A write occurs during the S-CS1# and R-WE# asserted overlap (tWP).
– The write begins with the latest transition of S-CS1# and R-WE# going low (R-UB# and/or R-LB# already asserted).
– The write ends at the earliest transition of S-CS1# or R-WE# goes high.
2.
tCW is measured from S-CS1# going low to the end of a write.
3.
tAS is measured from address valid to the beginning of a write.
4.
tWR is measured from the end of a write to the address change; tWR applied if a write ends as S-CS1# or R-WE# goes
high.
Figure 5.
SRAM Write Waveform
Number
Symbol
Parameter
Min
Max
Unit
Notes
High Z
Data In
Address Stable
Device
Address Selection
Standby
ADDRESSES
V
IH
V
IL
V
IH
V
IL
S-CS1#
V
IH
V
IL
V
OH
V
OL
V
IH
R-OE#
R-WE#
DATA
R- UB#, R-LB#
High Z
V
IH
V
IL
W1
W8
S-CS2
V
IH
V
IL
V
IH
W9
W6
W5
W2
W3
W4
W7
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