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參數(shù)資料
| 型號： | PDU54-100C4 |
| 英文描述： | Delay Line |
| 中文描述： | 延遲線 |
| 文件頁數(shù)： | 2/4頁 |
| 文件大?。?/td> | 263K |
| 代理商： | PDU54-100C4 |
PDU54
APPLICATION NOTES
ADDRESS UPDATE
The PDU54 is a memory device. As such,
special precautions must be taken when
changing the delay address in order to prevent
spurious output signals. The timing restrictions
are shown in Figure 1.
After the last signal edge to be delayed has
appeared on the OUT pin, a minimum time, T
OAX
,
is required before the address lines can change.
This time is given by the following relation:
T
OAX
= max { (A
i
- A
i-1
) * T
INC
, 0 }
where A
i-1
and A
i
are the old and new address
codes, respectively. Violation of this constraint
may, depending on the history of the input signal,
cause spurious signals to appear on the OUT
pin. The possibility of spurious signals persists
until the required T
OAX
has elapsed.
INPUT RESTRICTIONS
There are three types of restrictions on input
pulse width and period listed in the
AC
Characteristics
table. The
recommended
conditions are those for which the delay
tolerance specifications and monotonicity are
guaranteed. The
suggested
conditions are
those for which signals will propagate through the
unit without significant distortion. The
absolute
conditions are those for which the unit will
produce some type of output for a given input.
When operating the unit between the
recommended and absolute conditions, the
delays may deviate from their values at low
frequency. However, these deviations will
remain constant from pulse to pulse if the input
pulse width and period remain fixed. In other
words, the delay of the unit exhibits frequency
and pulse width dependence when operated
beyond the recommended conditions. Please
consult the technical staff at Data Delay Devices
if your application has specific high-frequency
requirements.
Please note that the increment tolerances listed
represent a design goal. Although most delay
increments will fall within tolerance, they are not
guaranteed throughout the address range of the
unit. Monotonicity is, however, guaranteed over
all addresses.
PACKAGE DIMENSIONS
16
15
14
13
19
18
17
PDU54-xx (Commercial DIP)
PDU54-xxM (Military DIP)
1.270
±
.010
1
2
3
4
5
6
7
8
12
11
10
9
.380
MAX.
.015 TYP.
.070 MAX.
.018 TYP.
1.100
±
.010
11 Equal spaces
each .100
±
.010
Non-Accumulative
.580
MAX.
.600
±
.005
.010
±
.002
Lead Material:
Nickel-Iron alloy 42
TIN PLATE
20
24
23
22
21
Doc #98004
3/18/98
DATA DELAY DEVICES, INC.
2
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PDU54-100M | Delay Line |
| PDU54-100MC4 | Delay Line |
| PDU54-1200 | Programmable Delay Line |
| PDU54-1200C4 | Delay Line |
| PDU54-1200M | Delay Line |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PDU54-100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Delay Line |
| PDU54-100MC4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Delay Line |
| PDU54-1200 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Programmable Delay Line |
| PDU54-1200C4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Delay Line |
| PDU54-1200M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Delay Line |
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