參數(shù)資料
型號(hào)： PDSP16515AA0AC
廠商： Mitel Networks Corporation
英文描述： Stand Alone FFT Processor
中文描述： 攻殼機(jī)動(dòng)隊(duì)FFT處理器
文件頁(yè)數(shù)： 16/27頁(yè)
文件大?。?/td> 289K
代理商： PDSP16515AA0AC
PDSP16515A
16
Figure 8. Three Device System with Separate Load, Transform, and Dump Operations
DUMP A1
DAV A
LFLG A
INEN B
LFLG B
DAV B
LOAD A1
LOAD A2
LOAD B1
LOAD B2
INEN A
DEF
DIS / DOS
INTERNAL
START
TRANSFORM A1
TRANSFORM B1
DUMP B1
TRANSFORM A2
In this operating mode the DIS and DOS strobes can often be
tied together, since a faster DOS strobe gives no improvement
in the sampling rates possible. This remains true even when
the output rate must be twice or four times the input rate due
to block overlapping. Options can then be used which
internally divide the DIS strobe by two or four, and thus allow
the input to be driven by the faster DOS strobe.
In this mode the LFLG goes in-active after 25%, 50%, or 100%
of the block has been loaded. When multiple transforms are
performed concurrently (for example 4 x 64) a LFLG transition
occurs at the relevant point whilst the first block in the group
is being loaded. LFLG then goes high again and returns low
at the overlap point in the last block. This double LFLG
transition allows two devices to support 50% block
overlapping, since the first transition from the first device can
be used to initiate the load procedure in the second device.
The second transition from the second device then initiates a
new load procedure in the first device. The additional edges
from each device have no effect since they occur when the
device they are driving is already doing a load operation.
In such a two device system supporting 50% overlaps the
inverted DAV from the first device must drive the DEN input of
the second device. The data dumping time is then shared
equally between both devices. The second device only
outputs data when the first has finished, but both dumps must
be finished in the time taken to load the group of blocks if only
one output processor is provided. Without the DAV/DEN
connection one device would only have had the time needed
to load half of one sub block in which to dump its data.
In a similar manner four devices will handle 75% overlaps
when concurrent multiple transforms are to be computed. The
second, third, and fourth devices make use of the first
transition, and ignore the second. The first device uses the
second transition from the last device, and ignores the first.
With the DAV/DEN connection each device will have one
quarter of the load time to dump its data when a single output
processor is provided .
More than two devices will provide increased performance for
multiple transforms with 50% overlapping, and more than four
devices will increase the performance with 75% overlapping.
External logic is then needed to ensure that each device only
uses the correct LFLG transition. Any device should only use
the negative LFLG transition from a previous device if its own
LFLG is low, and the LFLG output from the previous device
plus one is low.
Mode 2 (BITS 10:9 = 10)
This mode is suitable for all transform sizes, since separate
load, transform, and then dump operations occur. More
devices than required by Mode 1 are necessary to achieve a
given sampling rate, but the input and output rates can be any
value up to the full system clock rate. As with Mode 1,
additional output processors are needed to avoid the
sampling rate restriction imposed by block overlapping.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PDSP16515AA0ACBR 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Fast Fourier Transform Processor
PDSP16515AA0GC 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Stand Alone FFT Processor
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PDSP16515AB0AC 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:Stand Alone FFT Processor
PDSP16515AB0ACBR 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Fast Fourier Transform Processor
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