參數(shù)資料
型號(hào)： PDSP16510AC0GC
廠商： Mitel Networks Corporation
英文描述： Stand Alone FFT Processor
中文描述： 攻殼機(jī)動(dòng)隊(duì)FFT處理器
文件頁(yè)數(shù)： 7/23頁(yè)
文件大?。?/td> 94K
代理商： PDSP16510AC0GC
PDSP16510A MA
7
Characteristic
Data In set up Time
Data In Hold Time
INEN active going set up
INEN active Hold Time
INEN in-active Hold Time to ensure no load
INEN in-active going set up for no load operation
Delay to LFLG going active ( 30 pf load )
Delay to LFLG going in-active ( 30 pf load )
Min time to INEN low in edge mode
input and output buffering in addition to working memory. The
device is then configured in a mode with separate load,
transform and dump operations. The internal arrangement is
shown in Fig. 5. The support of an external input buffer is
needed if incoming samples are not to be lost whilst a
transform is in progress. This is loaded at the sample clock
rate and transferred to the FFT processor as quickly as
possible. In this mode the PDSP16510 always expects to
receive 1024 words, regardless of the amount of block over-
lapping. Data stored internally cannot be re-used when block
overlapping is required, and data from the external buffer must
be re-read as necessary.
Fig. 6 illustrates a typical 1024 point system with an input
buffer which supports complex input data. The input buffer
can be provided by a PDSP16540 Bucket Buffer without the
need for any external control logic. It supplies RAM for 1024
x 32 complex words, and allows transfers to the FFT Proces-
sor at the full system clock rate. The PDSP16540 also sup-
ports the standard 50% and 75% data block overlapping, but
in addition allows the user to define the amount of overlap to
within 32 words.
If no incoming data is to remain un-processed, the user
must ensure that the time taken to acquire sufficient data to
instigate a new transform is greater than or equal to the
transformation time itself. The latter can be calculated from
Table 1. Advanced Timing Information with Continuous Inputs.
Table 4, once the system clock rate has been defined. When
1024 point transforms are performed, both the time to read
data from the input buffer, and also the time to dump data,
must be included in the calculation to determine the minimum
time in which data can be loaded into the external buffer.
The peak transfer rate is limited by the characteristics of
the I/O circuits, but can be greater than the sampling rate
which is determined by the transform time. When load and
dump operations are not concurrent with transform operations
( as in the 1024 point modes ), then the maximum I/O rate is
equal to the system clock rate, . When other transform sizes
are specified, the sampling rate, S, is reduced by a factor F.
This is defined below where is in MHz and L is the system
clock low time in nanoseconds;
S = F, where F = 4
6 + 0.001L
F is typically 0.66 and applies to all transforms except for those
of 1024 points, even if INEN is driven such that concurrent
operations do not actually occur. If this causes a system
limitation in a single device application, then the device can be
configured for pseudo, Mode 2, multiple device operation.
Separate load, transform, and then dump operations will then
always occur, but DEN must be low when a transform is
Symbol
Min
Max
Units
T
SD
T
HD
T
SA
T
HA
T
HI
T
SI
T
FH
T
FL
T
ED
10
0
8
0
2
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
15
16510A
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