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參數(shù)資料
| 型號： | PDSP16488GC |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multipole Connector |
| 中文描述： | 二維卷積器的單芯片與線路延遲積分 |
| 文件頁數(shù)： | 10/33頁 |
| 文件大小： | 412K |
| 代理商： | PDSP16488GC |
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10
4 CLOCK
DELAY
LINE
DELAYS
0
DELAYS
Σ
WIDTH = S
+
4 CLOCK
DELAYS
0
DELAYS
0
DELAYS
ZERO
REG B3 = 1
DELAY = 0, DEFINED BY REG D3:2 = 00
REG D0 = 0
4 CLOCK
DELAY
LINE
DELAYS
0
DELAYS
Σ
WIDTH = S
+
4 CLOCK
DELAYS
D
DELAYS
0
DELAYS
REG B3 = 0
D = 4
1
S(N
2
1) DEFINED BY REG D3:2
REG D0 = 0
4 CLOCK
DELAY
LINE
DELAYS
0
DELAYS
Σ
WIDTH = S
+
D
DELAYS
0
DELAYS
4 CLOCK
DELAY
LINE
DELAYS
0/4
DELAYS
Σ
WIDTH = S
+
0
DELAYS
0
DELAYS
REG D0 = 0 IF S = 4,
OR REG D0 = 1 IF S = 8
Nth PDSP16488A IN THE ROW
4 CLOCK
DELAY
LINE
DELAYS
0/4
DELAYS
Σ
WIDTH = S
+
D
DELAYS
0
DELAYS
Nth PDSP16488A IN THE ROW
4 CLOCK
DELAY
LINE
DELAYS
0/4
DELAYS
Σ
WIDTH = S
+
D
DELAYS
0
DELAYS
REG B3 = 1
D = 4
1
S(N
2
1) DEFINED BY REG D3:2
Nth PDSP16488A IN THE ROW
INPUT
OUTPUT
PDSP16488A
PDSP16488A
PDSP16488A
REG B3 = 1
DELAY = 0, DEFINED BY REG D3:2 = 00
REG D0 = 0 IF S = 4,
OR REG D0 = 1 IF S = 8
REG B3 = 1
D = 4
1
S(N
2
1) DEFINED BY REG D3:2
REG D0 = 0 IF S = 4,
OR REG D0 = 1 IF S = 8
REG B3 = 0
D = 4
1
S(N
2
1) DEFINED BY REG D3:2
REG D0 = 0
Fig. 7 Multi-device delay paths
Delay Compensation for Large Windows
A large window is composed of several partial windows each of
which is implemented in an individual device. If necessary the partial
window must be padded with zero coefficients to become one of the
standard sizes. When constructing a large window it is necessary to
delay the expansion data inputs in order to compensate for growth
in the horizontal direction. Delays in the partial sums are also
necessary to compensate for the total pipeline delay needed to
produce the previous complete horizontal stripe.
Within each device in a horizontal stripe, apart from the first,
the expansion input must be delayed by the width of the partial
window, before it is added to the internal sum. Since partial
windows can only be 4 or 8 pixels wide, a delay of 4 or 8 pixel
clocks is needed. There is, however, an in-built delay of 4 pixels
in the inter device connection, and the PDSP16488A thus only
needs an option to delay the expansion input by an additional four
pixels.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PDSP16488AMA | Single Chip 2D Convolver with Integral Line Delays |
| PDSP16510AMAAC1R | Stand Alone FFT Processor |
| PDSP16510AA0AC | Stand Alone FFT Processor |
| PDSP16510AA0GC | Stand Alone FFT Processor |
| PDSP16510AC0AC | Stand Alone FFT Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PDSP16488GCPR | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Single Chip 2D Convolver with Integral Line Delays |
| PDSP16488MA | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Single Chip 2D Convolver with Integral Line Delays |
| PDSP16510 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:32K BUCKET BUFFER |
| PDSP16510A | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:I/Q Splitter/NCO |
| PDSP16510A/B0/GC | 制造商:Microsemi Corporation 功能描述:STAND ALONE FFT PROCESSOR 132CQFP - Bulk |
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