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參數(shù)資料
| 型號(hào)： | PDSP16330 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Pythagoras Processor(高速數(shù)字CMOS芯片（將笛卡爾數(shù)據(jù)轉(zhuǎn)換成Polar格式）) |
| 中文描述： | 畢達(dá)哥拉斯處理器（高速數(shù)字的CMOS芯片（將笛卡爾數(shù)據(jù)轉(zhuǎn)換成極格式）） |
| 文件頁(yè)數(shù)： | 3/9頁(yè) |
| 文件大?。?/td> | 173K |
| 代理商： | PDSP16330 |
PDSP16330/A/B
3
PIN DESCRIPTIONS
Symbol
Pin Name and Description
CLK
Clock:
Common Clock to device Registers. Register contents change on the rising edge of clock.
Both pins must be connected.
Clock Enable:
Clock Enable for X Port. The clock to the X port is enabled by a low level.
Clock Enable:
Clock Enable for Y Port The clock to the Y port is enabled by a low level.
X Data Input
Data presented to this input is loaded into the device by the rising edge of CLK.
X15 is the MSB
Y Data Input
Data presented to this input is loaded into the device by the rising edge of CLK.
Y15 is the MSB
M Data Output:
Magnitude data generated by the device is output on this port. Data changes on
the rising edge of CLK, M15 is the MSB. The weighting of M15 is determined by the Scale factor
selected .
P Data Output:
Phase data generated by the device is output on this port. Data changes on the
rising edge of CLK, P11 is the MSB. The weighting of P11 is
π
radians.
Output Enable:
Output Enable for M Port. The M Port is in a high impedance state when this input
is high.
Output Enable:
Output Enable for P Port. The P Port is in a high impedance state when this input
is high.
Format Select
This input selects the format of the Cartesian Data input on the X and Y ports.
This input is latched by the rising edge of CLK, and is applied at the same time as the data to
which it refers. A low !evel indicates that two’s complement data is applied, a high indicates
Sign-Magnitude
Scaling Control:
Control input for scaling of Magnitude Data. This input is latched by the rising
edge of CLK, and determines the scaling to be applied to the Magnitude result. The Scaling is
applied to the output data in the cycle following the cycle in which the control was latched.
Overflow:
Overflow flag. This signal becomes active if the scaling currently selected causes an
invalid value to be presented to the Magnitude output.
+
5V supply.
All Vcc pins must be connected.
CEX
CEY
X15-X0
Y15-Y0
M15-M0
P11-P0
OEM
OEP
FORM
S1-S0
OVR
Vcc
GND
0V supply.
All GND pins must be connected.
2's Complement
7FFF
.
.
.
0001
0000
FFFF
.
.
.
8001
Sign Magnitude
7FFF
.
.
.
0001
0000
8000
.
.
.
FFF
INPUT DATA RANGE
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| PDSP16330B | Pythagoras Processor(高速數(shù)字CMOS芯片（將笛卡爾數(shù)據(jù)轉(zhuǎn)換成Polar格式）) |
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| PDSP16330A | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Pythagoras Processor |
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| PDSP16330A0AC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Other/Special/Miscellaneous Converter |
| PDSP16330A0GG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Other/Special/Miscellaneous Converter |
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