參數(shù)資料
型號: PDSP16330 MC
廠商: Mitel Networks Corporation
英文描述: Pythagoras Processor(高速數(shù)字CMOS芯片(將笛卡爾數(shù)據(jù)轉(zhuǎn)換成Polar格式))
中文描述: 畢達(dá)哥拉斯處理器(高速數(shù)字的CMOS芯片(將笛卡爾數(shù)據(jù)轉(zhuǎn)換成極格式))
文件頁數(shù): 5/10頁
文件大?。?/td> 123K
代理商: PDSP16330 MC
PDSP16330 MC
5
Characteristic
*
Input data setup to clock rising edge
Input data Hold after clock rising edge
CEX, CEY Setup to clock rising edge
CEX, CEY Hold aher clock rising edge
FORM, S1:0 Setup to clock rising edge
FORM, S1:0 Hold after clock rising edge
Clock rising edge to valid data
Clock period
Clock high time
Clock low time
Latency
OEM, OEP low to data high data valid
OEM, OEP low to data low data valid
OEM, OEP high to data high impedance
OEM, OEP low to data high impedance
Vcc current (TTL input levels)
Vcc current (CMOS input levels)
SWITCHING CHARACTERISTICS
Min.
15
2
30
0
15
7
5
100
25
25
24
Max.
40
24
30
30
30
30
110
70
PDSP16330
Value
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cycles
ns
ns
ns
ns
mA
mA
Conditions
2 x LSTTL + 20pF
2 x LSTTL + 20pF
2 x LSTTL + 20pF
2 x LSTTL + 20pF
2 x LSTTL + 20pF
V
= Max
Outputs unloaded
Clock freq. = Max
V
= Max
Outputs unloaded
Clock freq. = Max
Sub-
group
9,10,11
ABSOLUTE MAXIMUM RATINGS
Supply voltage, V
cc
Input voltage, V
IN
Output voltage, V
Clamp diode current per pin, I
(see Note 2)
Static discharge voltage (HMB), V
500V
Storage temperature. T
-65
°
C to + 150
°
C
Ambient temperature with
power applied T
:
Military -55
°
C to + 125
°
C
Package power dissipation P
1200mW
Junction temperature 150
°
C
-0.5V to + 7.0V
-0.5V to VCC + 0.5V
-0.5V to VCC + 0.5V
±
18mA
THERMAL CHARACTERISTICS
Package Type
GC
θ
JC
°
C/W
12
NOTES
1.
Functional operatlon under these conditions is not implied.
2.
Maximum dissipation or 1 second should not be exceeded;
only one output to be tested at any one time.
3.
Exposure to Absolute Maximum Ratings for extended
periods may affect device reliability
Exceeding these ratings may cause permanent damage.
NOTES
1.
2.
3.
4.
LSTTL is equivalent to I
= 20
μ
A, I
= -0.4mA
Current is defined as negative into the device
CMOS input levels are defined as: V
= V
- 0.5V, V
IL
= +0.5V
All parameters marked * are tested during production.
Parameters marked are guaranteed by design and characterisation.
All timings are dependent on silicon speed. This speed is tested by measuring clock period.
This guarantees all other timings by characterisation and design.
5.
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