1
Supersedes version DS3708 - 2.4 September 1996
DS3708 - 3.1 November 1998
PDSP16318/PDSP16318A
Complex Accumulator
Advance Information
The PDSP16318/A contains two independent 20-bit
Adder/Subtractors combined with accumulator registers and
shift structures. The four port architecture permits full 20MHz
throughout in FFT and filter applications.
Two PDSP16318As combined with a single PDSP16112A
Complex Multiplier provide a complete arithmetic solution for
a Radix 2 DIT FFT Butterfly. A new complex Butterfly result
can be generated every 50ns allowing 1K complex FFTs to be
executed in 256
μ
s.
FEATURES
I
I
I
I
I
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Full 20MHz Throughout in FFT Applications
Four Independent 16-bit I/O Ports
20-bit Addition or Accumulation
Fully Compatible with PDSP16112 Complex Multiplier
On Chip Shift Structures for Result Scaling
Overflow Detection
Independent Three-State Outputs and Clock
Enables for 2 Port 20MHz Operation
1.4 micron CMOS
500mW Maximum Power Dissipation
100 CQFP package
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APPLICATIONS
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High speed Complex FFT or DFTs
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Complex Finite Impulse Response (FIR) Filtering
I
Complex Conjugation
I
Complex Correlation/Convolution
ASSOCIATED PRODUCTS
PDSP16112
16 x 12 Complex Multiplier
PDSP16116
16 x 16 Complex Multiplier
PDSP1601
ALU and Barrel Shifter
PDSP16330
Pythagoras Processor
Fig.1 Pin connections - Top view (GC100)
GC100
ORDERING INFORMATION
Industrial (-40
°
C to +85
°
C)
PDSP16318A/IG/GC1R
Military (-55
°
C to +125
°
C)
PDSP16318/MC/GC1R
(20MHz - QFP)
(10MHz - QFP
MIL STD 883C Screened)
N.B. Further details of the Military grade part are available
in a separate datasheet
Fig. 2 PDSP16318 simplified block diagram
REG
DELAY
A
B
B
A
SHIFT
REG
C
A
B
SHIFT
REG
D
REG