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參數(shù)資料
| 型號(hào)： | PDSP16318 MC |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Complex Accumulator(復(fù)雜累加器（由兩個(gè)獨(dú)立的20位加法器/減法器組成）) |
| 中文描述： | 復(fù)雜累加器（復(fù)雜累加器（由兩個(gè)獨(dú)立的20位加法器/減法器組成）） |
| 文件頁(yè)數(shù)： | 2/10頁(yè) |
| 文件大?。?/td> | 123K |
| 代理商： | PDSP16318 MC |
PDSP16318 MC
2
A
B
SHIFT
REG
REG
D
B
A
SHIFT
REG
D
MUX
MUX
MUX
A REG
CYCLE
DELAY
REG
REG
A
16
16
8
20
20
20
16
16
16
16
20
16
16
B
20
20
20
MS
REG
ASI
OED
CLR
OVR
OEC
S2:0
ASR
DEL
CEA
CLK
Fig.2 Block diagram
FUNCTIONAL DESCRIPTION
The PDSP16318 is a Dual 20-bit Adder/Subtractor
configured to supprt Complex Arithmetic. The device may be
used with each of the adders allocated to real or imaginary
data (e.g. Complex Conjugation), the entire device allocated
to Real or Imaginary Data (e.g. Radix 2 Butterflys) or each of
the adders configured as accumulators and allocated to real
or imaginary data (Complex Filters). Each of these modes
ensures that a full 10MHz throughput is maintained through
both adders, the first and last mode illustrating true Complex
operation, where both real and imaginary data is handled by
the single device.
Both Adder/Subtractors may be controlled
independently via the ASR and ASI inputs. These controls
permit A + B, A - B, B - A or pass A operations, where the A
input to the Adder is derived from the input multiplexer. The
CLR control line allows the clearing of both accumaltor
registsers. The two multiplexers may be controlled via the MS
inputs, to select either new input data, or fed-back data from
the accumulator registers. The PDSP16318 contains an 8-
cycle deskew register selected via the DEL control. This
deskew register is used in the FFT applications to ensure
correct phasing of data that has not passed through the
PDSP16112 Complex Multiplier.
The 16-bit outputs from the PDSP16318 are derived from
the 20-bit result generated by the Adders. The three bit S2:0
input selects eight different shifted output formats ranging
from the most significant 16 bits of the 20-bit data, to the least
significant 13 bits of the 20-bit data. In this mode the 14th, 15th
and 16th bits of the output are set to zero. The shift selected
is applied to both adder outputs, and determines the function
of the OVR flag. The OVR flag becomes active when either of
the two adders produces a result that has more significant
digits than the MSB of the 16-bit output from the device. In this
manner all cases when invalid data appears on the output are
flagged.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PDSP16318GC1R | CAT5E PATCH CORD SNAGLESS, GREEN 100FT |
| PDSP16318MC | PDSP16256GC1R |
| PDSP16318A | PDSP16256GC1R |
| PDSP16318 | Complex Accumulator(復(fù)雜累加器（由兩個(gè)獨(dú)立的20位加法器/減法器組成）) |
| PDSP16318A | Complex Accumulator(復(fù)雜累加器（由兩個(gè)獨(dú)立的20位加法器/減法器組成）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PDSP16330 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Pythagoras Processor |
| PDSP16330A | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Pythagoras Processor |
| PDSP16330A/IG/GC1R | 制造商:Microsemi Corporation 功能描述:PYTHAGORAS PROCESSOR 100PQFP - Tape and Reel |
| PDSP16330A0AC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Other/Special/Miscellaneous Converter |
| PDSP16330A0GG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Other/Special/Miscellaneous Converter |
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