參數(shù)資料
型號(hào)： PDSP16256GC
廠商： Mitel Networks Corporation
英文描述： Programmable FIR Filter
中文描述： 可編程FIR濾波器
文件頁(yè)數(shù)： 19/28頁(yè)
文件大?。?/td> 423K
代理商： PDSP16256GC
PDSP16256
19
Control Register
The internal operation of the PDSP16256 is
controlled by the status of a 16-bit control register. In
the dual filter modes both networks are controlled by
the same register. The significance of the various
bits are shown in Table 6. Tables 7 and 8 define the
control register bit interdependence for the filter and
bank swapping modes.
The control register is double buffered. This allows
the writing of a new control word without affecting the
current operation of the device. To activate the new
control register after it has been written to the device
the bank swap signal must be toggled. After a reset
the active control register is loaded directly and bank
swap need not be used.
Control
Register
Bits
7
0
1
1
X
Function
6
X
0
1
X
5
0
0
0
1
Control by input pin
Lower bank selected
Upper bank selected
Swap on every sample clock
Bits
Decode
Function
15
15
0
1
00
01
10
Dual filter mode
Single filter mode
Sample rate is the system clock
Sample rate is half the system clock
Sample rate is quarter the system
clock
Sample rate is eighth the system clock
Output rate equals the input rate
Decimate-by-two
Intermediate device
Interface device
Termination device
Single device
These bits MUST be at logical zero
Bank swap is controlled by input pin
Bank swap is controlled by Bit 6
Lower bank if bit 7 is set
Upper bank if bit 7 is set
This bit must be at logical zero
Two independent filters
Two filters in cascade
These bits MUST be at logical zero
14:13
14:13
14:13
14:13
12
12
11:10
11:10
11:10
11:10
9:8
7
7
6
6
5
4
4
3:0
11
0
1
00
01
10
11
00
0
1
0
1
0
1
Control
Register
Bits
15
0
0
1
Function
4
0
1
X
Two independent filters
Two filters in cascade
Single Filter
Table 8 Control register bank swap bits
Table 7 Control register filter mode bits
Table 6 Control register bit allocation
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