參數(shù)資料
型號(hào)： PDSP16256B0
廠商： Mitel Networks Corporation
英文描述： Programmable FIR Filter
中文描述： 可編程FIR濾波器
文件頁(yè)數(shù)： 7/28頁(yè)
文件大?。?/td> 423K
代理商： PDSP16256B0
PDSP16256
7
Figure. 5 Filter network diagram
Single Filter Options
When operating as a single filter the device accepts data
on the 16-bit DA bus at the selected sample rate, see
Figs. 5 and 6. Results are presented on the 32-bit F bus,
which may be tristated using the
OEN
input. Signal
OEN
is
registered onto the device and does not therefore take
effect until the first SCLK rising edge. Devices may be
cascaded this allows filters with more taps than available
from a single device. To accomplish this two further
buses are utilised. The DB bus presents the input data to
the next device in cascade after the appropriate delay,
while, partial results are accepted on the X bus.
Single filter mode is selected by setting control register bit
15 to a one. The required filter length is then selected
using control register bits 14 and 13 as summarised in
Table 3. The options define the number of times each
multiplier accumulator is used per sample clock period.
This can be once, twice, four times, or eight times.
In addition a normal/decimate bit (CR12) allows the filter
length to be doubled at any sample rate. This is possible
when the filter coefficients are selected to produce a low
pass filter, since the filtered output would then not contain
the higher frequency components present in the input.
The Nyquist criterion, specifying that the sampling rate
must be at least double the highest frequency compo-
nent, can still then be satisfied even though the sampling
rate has been halved.
The system clock latency for a single device is shown in
Table 3. This is defined as the delay from a particular data
sample being available on the input pins to the first result
including that input appearing on the output pins. It does
not include the delay needed to gather N samples, for an
N tap filter, before a mathematically correct result is
obtained.
CR
Input
Rate
Output
Rate
Filter
Length
Setup
Latency
14 13 12
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
SCLK
SCLK
SCLK/2
SCLK/2
SCLK/4
SCLK/4
SCLK/8
SCLK
SCLK/2
SCLK/2
SCLK/4
SCLK/4
SCLK/8
SCLK/8
16 Taps
32 Taps
32 Taps
64 Taps
64 Taps
128 Taps
128 Taps
16
17
16
18
20
24
24
Table 3 Single Filter options
Figure. 6 Single Filter bus utilisation
DA15:0
F31:0
OEN
NETWORK
A
NETWORK
B
DUAL
MODE
SINGLE
MODE
MUX
DB15:0
X31:0
DATA
DELAY LINE
DATA
OUT
COEFF
RAM
ADDER
Z
2
1
DATA
DELAY LINE
COEFF
RAM
ADDER
Z
2
1
DATA
DELAY LINE
COEFF
RAM
ADDER
Z
2
1
DATA
DELAY LINE
COEFF
RAM
ADDER
Z
2
1
ACCUMULATE
EXPANSION
IN
DATA
IN
RESULT
OUT
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PDSP16256B0AC 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Digital Filter
PDSP16256B0GC 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Digital Filter
PDSP16256C0 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:Programmable FIR Filter
PDSP16256C0GC 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Digital Filter
PDSP16256GC 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:Programmable FIR Filter
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