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參數(shù)資料
| 型號： | PDSP16256AC |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Programmable FIR Filter |
| 中文描述： | 可編程FIR濾波器 |
| 文件頁數(shù)： | 9/28頁 |
| 文件大?。?/td> | 423K |
| 代理商： | PDSP16256AC |
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PDSP16256
9
Dual Indipendant Filter Options
When operating as two independent filters the device
accepts 16 bit data on both the DA and DB buses at the
selected sample rate, see Fig. 8. Results are available
from both the F and X buses. The F bus may be tristated
using the
OEN
input. Signal
OEN
is registered onto the
device and does not therefore take effect until the first
SCLK rising edge
Each filter must be configured in the same manner, and
multiple device expansion is not possible due to the pin
re-organization. The latter requirement can, of course,
still be satisfied by several devices configured as single
filters.
Dual independent filter mode is selected by setting
control register bits 15 and 4 to a zero. The required filter
length is selected using control register bits 14 and 13 as
summarised in Table 4, which also shows the resulting
latency. As in single filter mode normal or decimate-by-
two operation can be selected using control register bit
12.
Dual Cascaded Filter Options
When operating as two cascaded filters the device ac-
cepts 16 bit data on the DA bus at the selected sample
rate. Results are presented on the 32-bit X bus, see Fig.
9. Each filter must be configured in the same manner.
Multiple device expansion is not possible in this mode.
Dual cascaded filter mode is selected by setting control
register bit 15 to a zero and bit 4 to a one. The required
filter length is selected using control register bits 14 and
13 as summarised in Table 4, which also shows the
resulting latency. The decimate-by-two option is not
available in this mode.
The data for the second filter network is extracted as the
middle 16 bits from the first networks accumulated result.
For successful operation the first filter network must have
unity gain. See the section on filter accuracy for more
details.
The cascade option is used to increase the stop band
rejection in a practical filter application. Theoretically,
increasing the number of taps in an FIR filter will increase
the stop band rejection, but this assumes floating point
calculations with no accuracy limitations. In practice, with
fixed point arithmetic, better performance is achieved
with two smaller filters in series.
CR
Input
Rate
Output
Rate
Filter
Length
Setup
Latency
Ind
16
17
16
18
20
24
24
141312
Cas
27
-
28
-
36
-
40
0 0 0
0 0 1
0 1 0 SCLK/2
0 1 1 SCLK/2
1 0 0 SCLK/4
1 0 1 SCLK/4
1 1 0 SCLK/8
SCLK
SCLK
SCLK
SCLK/2
SCLK/2
SCLK/4
SCLK/4
SCLK/8
SCLK/8
8 Taps
16 Taps
16 Taps
32 Taps
32 Taps
64 Taps
64 Taps
Table 4. Dual Filter options
Figure. 9 Dual cascaded filter bus utilisation
Figure. 8 Dual independent filter bus utilisation
DA15:0
F31:0
OEN
NETWORK
A
NETWORK
B
DUAL
MODE
SINGLE
MODE
MUX
DB15:0
X31:0
DA15:0
F31:0
OEN
NETWORK
A
NETWORK
B
DUAL
MODE
SINGLE
MODE
MUX
DB15:0
X31:0
相關PDF資料 |
PDF描述 |
|---|---|
| PDSP16256AC1R | Programmable FIR Filter |
| PDSP16256B0 | Programmable FIR Filter |
| PDSP16256GC | Programmable FIR Filter |
| PDSP16256MC | Programmable FIR Filter |
| PDSP16318 MC | Complex Accumulator(復雜累加器（由兩個獨立的20位加法器/減法器組成）) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PDSP16256AC0AC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Filter |
| PDSP16256AC0GC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Filter |
| PDSP16256AC1R | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Programmable FIR Filter |
| PDSP16256AMAGCPR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Filter |
| PDSP16256B0 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Programmable FIR Filter |
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