參數(shù)資料
型號(hào)： PDSP16256
廠商： Mitel Networks Corporation
英文描述： Programmable FIR Filter
中文描述： 可編程FIR濾波器
文件頁(yè)數(shù)： 10/28頁(yè)
文件大?。?/td> 423K
代理商： PDSP16256
PDSP16256
10
Filter Accuary
Input data and coefficients are both represented by 16-
bit two’s complement numbers. The coefficients are
converted to twelve bits by rounding towards zero. This
is achieved as follows. If the coefficient is positive then
the least significant 4 bits are discarded. If the coefficient
is negative then the logical ‘OR’ of the least significant 4
bits are added to the remainder of the word. Twelve bit
coefficients can be used directly provided the least
significant four bits are set to zero.
The FIR filter results are calculated using a multiplier
accumulator structure as shown in Fig. 10. The trunca-
tion and word growth allowed for in the data path are
explained in Fig. 10. The 16-bit data and 12-bit coeffi-
cient inputs (each with one sign bit before the binary
point), are presented to the multiplier. This produces a
28-bit result with two bits before the binary point. Produc-
ing the full 28-bit result ensures that if both the data and
coefficients are set to logic 1 a valid result is generated.
Prior to entering the accumulator the least significant 4
bits of the multiplier result are truncated and the resulting
24 bits sign extended to 32 bits. The final accumulator
result is 32 bits with 10 bits before the binary point. Thus
9 bits of word growth are allowed within the accumulator.
All accumulator bits are made available on the output
pins.
In cascade mode the middle 16 bits from the network A
accumulator are fed round to the network B data inputs,
see Fig. 11.
COEFFICIENT
ADDER
INPUT DATA
ACCUMULATOR
RESULT
S
8
7
6
5
4
3
2
1
0
S
S
S
S
S
S
S
S
S
0
S
0
-
26
S
S
ACCUMULATOR RESULT
These bits are passed to filter network B during cascade mode
-
25
-
24
-
23
-
22
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
-
22
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
-
22
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
-
15
ACCUMULATOR RESULT
MULTIPLIER RESULT
COEFFICIENT
INPUT DATA
Sign extended to 32 bits, least significant 4 bits truncated
Multiplication producing a 28-bit result
Figure. 10 Multiplier Accumulator
Figure. 11 Filter accuracy
相關(guān)PDF資料
PDF描述
PDSP16256A Programmable FIR Filter
PDSP16256AC Programmable FIR Filter
PDSP16256AC1R Programmable FIR Filter
PDSP16256B0 Programmable FIR Filter
PDSP16256GC Programmable FIR Filter
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PDSP16256/A 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:I/Q Splitter/NCO
PDSP16256/BO/AC 制造商:Microsemi Corporation 功能描述:
PDSP16256_98 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Programmable FIR Filter
PDSP16256A 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Programmable FIR Filter
PDSP16256A/C0/AC 制造商:Microsemi Corporation 功能描述:ZARPDSP16256A/C0/AC I.C.
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