PDSP16256
8
SPEED MODE 0
(Data input and output at f
SCLK
) CR14:13 = 00, CR12 = 0. CLKOP held high.
1
2
3
A
B
C
16
17
18
A
′
B
′
C
′
31
32
33
A
′′
B
′′
C
′′
34
35
D
′′
E
′′
SCLK
FEN
DA15:0
F31:0
CLKOP
SPEED MODE 1
(Data input and output at half f
SCLK
) CR14:13 = 01, CR12 = 0
1
2
3
A
B
16
17
18
A
′
B
′
78
79
80
A
′′
B
′′
C
′′
81
82
SCLK
FEN
DA15:0
F31:0
CLKOP
First data point (A)
is read on edge 1
First valid result
including data point (A)
available after edge 16
Valid result contains
the first 16 data points
available after edge 31
First data point (A)
is read on edge 1
First valid result
including data point (A)
available after edge 16
Valid result contains
the first 32 data points
available after edge 78
SPEED MODE 2
(Data input and output at a quarter f
SCLK
) CR14:13 = 10, CR12 = 0
1
2
3
A
B
20
21
22
A
′
B
′
272 273
A
′′
B
′′
SCLK
FEN
DA15:0
F31:0
CLKOP
First data point (A)
is read on edge 1
First valid result
including data point (A)
available after edge 20
Valid result contains
the first 64 data points
available after edge 272
4
5
23
24
274 275 276
SPEED MODE 3
(Data input and output at an eighth f
SCLK
) CR14:13 = 11, CR12 = 0
1
2
3
A
B
24
25
26
A
′
B
′
1040
A
′′
SCLK
FEN
DA15:0
F31:0
CLKOP
First data point (A)
is read on edge 1
First valid result
including data point (A)
available after edge 24
Valid result contains
the first 128 data points
available after edge 1040
4
5
27
28
1041 10421043
6
7
8
9
29
30
31
32
SPEED MODE 1 Decimating
(Data input at half
f
SCLK
and output at a quarter f
SCLK
) CR14:13 = 01, CR12 = 1.
1
2
3
A
B
18
19
20
B
′
142
143
144
145
SCLK
FEN
DA15:0
F31:0
CLKOP
First data point (A)
is read on edge 1
First valid result
including data point (A)
available after edge 18
Valid result contains
the first 64 data points
available after edge 142
21
22
B
′′
Figure. 7 Single Filter timing diagrams