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參數(shù)資料
| 型號(hào)： | PDSP16116AB0GG |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | 16 X 16 Bit Complex Multiplier |
| 中文描述： | 16 × 16位乘法器復(fù)雜 |
| 文件頁數(shù)： | 9/17頁 |
| 文件大?。?/td> | 270K |
| 代理商： | PDSP16116AB0GG |
PDSP16116
9
OSEL1 :0
The outputs from the device are selected by the OSEL0
and OSEL1 instruction bits. These controls allow selection
of the output combination during the current cycle (they are
not registered). There are four possible output configurations
that allow either complex outputs of the most or least signifi-
cant bytes, or real or imaginary outputs of the full 32-bit word
(see Table 4). OSEL0 and OSEL1 should both be tied low
when in BFP mode.
BFP MODE FFT APPLICATION
The PDSP16116 may be used as the main arithmetic unit of
the butterfly processor, which will allow the following FFT bench-
marks:
G
1024-point complex radix 2 transform in 517
μ
s
G
512-point complex radix 2 transform in 235
μ
s
G
256-point complex radix 2 transform in 106
μ
s
In addition, with pin MBFP tied high, the BFP circuitry within
the PDSP16116 can be used to adaptively rescale data through-
out the course of the FFT so as to give high-resolution results.
The BFP system on the PDSP16116 can be used with any vari-
ation of the radix 2 decimation-in-time (DIT) FFT, for example,
the constant geometry algorithm, the in-place algorithm etc. An
N-point Radix 2 DIT FFT is split into log(N) passes. Each pass
consists of N/2 ‘butterflies’, each performing the operation:
A
′
= A
1
BW
B
′
= A
2
BW
Where W is the complex coefficient and A and B are the
complex data. Fig.4 illustrates how a single PDSP16116 may
be combined with two PDSP1601s and two PDSP16318s to
form a complete BFP butterfly processor. The PDSP16318s are
used to perform the complex addition and subtraction of the
butterfly operation, while the PDSP1601s are used to match
the data path of the A-word to the pipelining and shifting opera-
tions within the PDSP16116.
For more information on the theory and construction of this
butterfly processor, refer to application note AN59.
BFP MODE OPERATION
The BFP mode on the PDSP16116 is intended for use in the
FFT application described above, that is, it is intended to pre-
vent data degradation during the course of an FFT calculation.
The operation of the PDSP16116-based BFP buttertly proces-
sor (see Fig.4) is described below.
The Block Floating Point System
A block floating point system is essentially an ordinary inte-
ger arithmetic system with some additional logic, the purpose of
which is to lend the system some of the enormous dynamic
range afforded by a true floating point system without suffering
the corresponding loss in perlormance.
The initial data used by the FFT should all have the same
binary arithmetic weighting. In other words, the binary point
should occupy the same position in every data word as is nor-
mal in integer arithmetic. However, during the course of the FFT,
a variety of weightings are used in the data words to increase
the dynamic range available. This situation is similar to that within
a true floating point system, though the range of numbers rep-
resentable is more limited. In the BFP system used in the
PDSP16116, there are, within any one pass of the FFT, four
possible positions of the binary point wihin the integer words. To
record the position of its binary point, each word has a 2-bit
word tag associated with it. By way of example, in a particular
pass the following four positions of binary point may be avail-
able, each denoted by a certain value of word:
XX·XXXXXXXXXXXX word tag = 00
XXX·XXXXXXXXXXX word tag = 01
XXXX·XXXXXXXXXX word tag = 10
XXXXX·XXXXXXXXX word tag = 11
At the end of each constituent pass of the FFT, the positions
of the binary point supported may change to reflect the trend of
data increase or decreases in magnitude. Hence, in the pass
following that of the above example, the four positions of binary
point supported may be changed to:
XX·XXXXXXXXXXXX word tag = 00
XXX·XXXXXXXXXXX word tag = 01
XXXX·XXXXXXXXXX word tag = 10
XXXXX·XXXXXXXXX word tag = 11
This variation in the range of binary points supported from
pass to pass (i.e. the movement of the binary point relative to its
position in the original data) is recorded in the GWR. Thus, the
position of the binary point can be determined relative to its ini-
tial position by modifying the value of GWR by WTOUT for a
given word as shown in Table 6. As an example, if GWR=01001
and WTOUT=10 then the binary point has moved 10 places to
the right of its original position.
PDSP16116/A
XR
XI
YR
YI
BR
BI
WR
WI
WTA
WTB
EOPSS
SOBFP
PR
PI
PDSP1601/A
A
C
AI
AI15:13
PDSP1601/A
A
C
AR
AR15:13
PDSP16318/A
A
B
C
D
PDSP16318/A
B
A
C
D
WTOUT GWR
A
′
R
A
′
I
B
′
R
B
′
I
DAR
DAI
SFTA
SFTA
SFTR
SFTR
OER
OEI
Fig. 4 FFT butterfly processor
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| PDSP16116AC0GG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multiplier |
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