參數(shù)資料
型號(hào)： PDSP16116AA0AC
廠商： Mitel Networks Corporation
英文描述： 16 X 16 Bit Complex Multiplier
中文描述： 16 × 16位乘法器復(fù)雜
文件頁(yè)數(shù)： 11/17頁(yè)
文件大?。?/td> 270K
代理商： PDSP16116AA0AC
PDSP16116
11
CLK
n
2
4
n
2
3
n
2
2
n
2
1
n
2
5
A
′
, B
′
, BTOUT
SOBFP
EOPSS
A, B, W,
WTA, WTB
GWR
2
3
4
5
6
7
n
2
1
2
3
2
3
1
n
1
1
n
START OF
FIRST PASS
END OF FIRST PASS/
START OF NEXT PASS
(MINIMUM NUMBER OF
LAY CYCLES SHOWN).
PERIOD BETWEEN
OTHER INTERMEDIATE
PASSES IS SIMILAR.
NOTES
1. 1 = FIRST CYCLE OF DATA IN PASS
2. n = LAST CYCLE OF DATA IN PASS
In practice, data output may never approach the theoretical
maximum. Hence, it may be worthwhile to try various universal
exponents and choose the one best suited to the particular ap-
plication.
Data is output from the butterfly processor with a two-part
exponent: the 5-bit GWR applicable to all data words from a
given FFT and a 2-bit WTOUT associated with each individual
dataword. To find the complete exponent for a given word, the
GWR for that FFT must be modified by its WTOUT as shown in
Table 6. The result is the number of places the binary point has
shifted to the right during the course of the FFT.
This value must be compared with the universal exponent to
determine the shift required. This is done by subtracting it from
the universal exponent. The number of places to be shifted is
equal to the difference between the two exponents. The shift
can be implemented in a PDSP1601/A (the shift value is fed
into the SV port).
As FFT data consists of real and imaginary parts, either two
PDSP1601/As must be used (controlled by the same logic) or a
single PDSP1601/A could be used handling real and imaginary
data on alternate cycles (using the same instructions for both
cycles).
An example of an output normalisation circuit is shown
in Fig.8. Only 4-bit data paths are used in calculating the
shift. This means that we must be able to trap very small
values negative of GWR and force a 15-bit right shift in
such cases.
NB
It is easier to simply add the word tag to the exponent for the
purpose of determing the shift required, instead of modifying it
according to Table.6. To compensate for this, the universal ex-
ponent may be increased by one.
Fig. 8 Output normalisation circuit
4-BIT ADDER
GWR
WTOUT
4-BIT SUBTRACTOR
UNIVERSAL
EXPONENT
4-BIT MUX
1111
SIGN
BIT
16-BIT DATA
PDSP1601
C PORT
SV PORT
B PORT
ASRSV
NORMALISED OUTPUT DATA
Fig. 7 Use of the BFP control signals
相關(guān)PDF資料
PDF描述
PDSP16116AB0AC 16 X 16 Bit Complex Multiplier
PDSP16116AB0GG 16 X 16 Bit Complex Multiplier
PDSP16116 16 X 16 Bit Complex Multiplier
PDSP16116AMCGGDR 16 X 16 Bit Complex Multiplier
PDSP16116BB0AC 16 X 16 Bit Complex Multiplier
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PDSP16116AA0GG 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multiplier
PDSP16116AB0AC 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:16 X 16 Bit Complex Multiplier
PDSP16116AB0GG 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:16 X 16 Bit Complex Multiplier
PDSP16116AC0AC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multiplier
PDSP16116AC0GG 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multiplier
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