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CHAPTER 5 CLOCK GENERATOR
User’s Manual U16228EJ2V0UD
121
Remarks 1.
MCM0: Bit 0 of the main clock mode register (MCM)
2.
f
X
: Main system clock oscillation frequency (X1 input clock oscillation frequency or Ring-OSC clock
oscillation frequency)
3.
f
R
: Ring-OSC clock oscillation frequency
4.
f
XP
: X1 input clock oscillation frequency
5.
f
XT
: Subsystem clock oscillation frequency
The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/KE1. Therefore, the relationship
between the CPU clock (f
CPU
) and minimum instruction execution time is as shown in the Table 5-2.
Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution Time
Minimum Instruction Execution Time: 2/f
CPU
CPU Clock (f
CPU
)
X1 Input Clock
(at 10 MHz Operation)
Note
Ring-OSC Clock
(at 240 kHz (TYP.) Operation)
Note
Subsystem Clock
(at 32.768 kHz Operation)
f
X
0.2
μ
s
8.3
μ
s (TYP.)
f
X
/2
0.4
μ
s
16.6
μ
s (TYP.)
f
X
/2
2
0.8
μ
s
33.2
μ
s (TYP.)
f
X
/2
3
1.6
μ
s
66.4
μ
s (TYP.)
f
X
/2
4
3.2
μ
s
132.8
μ
s (TYP.)
f
XT
/2
122.1
μ
s
Note
The main clock mode register (MCM) is used to set the CPU clock (X1 input clock/Ring-OSC clock) (see
Figure 5-4
).
(2) Ring-OSC mode register (RCM)
This register sets the operation mode of Ring-OSC.
This register is valid when “Can be stopped by software” is set for Ring-OSC by a mask option, and the X1 input
clock or subsystem clock is selected as the CPU clock. If “Cannot be stopped” is selected for Ring-OSC by a
mask option, settings for this register are invalid.
RCM can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 5-3. Format of Ring-OSC Mode Register (RCM)
Address: FFA0H After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
<0>
RCM
0
0
0
0
0
0
0
RSTOP
RSTOP
Ring-OSC oscillating/stopped
0
Ring-OSC oscillating
1
Ring-OSC stopped
Caution Make sure that the bit 1 (MCS) of the main clock mode register (MCM) is 1 before
setting RSTOP.