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CHAPTER 5 CLOCK GENERATOR
User’s Manual U16228EJ2V0UD
124
(5) Oscillation stabilization time counter status register (OSTC)
This is the status register of the X1 input clock oscillation stabilization time counter. If the Ring-OSC clock is used
as the CPU clock, the X1 input clock oscillation stabilization time can be checked.
OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset is released (reset by RESET input, POC, LVI, clock monitor, and WDT), the STOP instruction,
MSTOP = 1, and MCC = 1 clear OSTC to 00H.
Figure 5-6. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFA3H After reset: 00H R
Symbol
7
6
5
4
3
2
1
0
OSTC
0
0
0
MOST11
MOST13
MOST14
MOST15
MOST16
MOST11
MOST13
MOST14
MOST15
MOST16
Oscillation stabilization time status
1
0
0
0
0
2
11
/f
XP
min. (204.8
μ
s min.)
1
1
0
0
0
2
13
/f
XP
min. (819.2
μ
s min.)
1
1
1
0
0
2
14
/f
XP
min. (1.64 ms min.)
1
1
1
1
0
2
15
/f
XP
min. (3.27 ms min.)
1
1
1
1
1
2
16
/f
XP
min. (6.55 ms min.)
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and
remain 1.
2. If the STOP mode is entered and then released while the Ring-OSC is being used
as the CPU clock, set the oscillation stabilization time as follows.
Desired OSTC oscillation stabilization time
≤
Oscillation stabilization time
set by OSTS
The X1 oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. Note, therefore, that only the status up to the
oscillation stabilization time set by OSTS is set to OSTC after STOP mode is
released.
3. The wait time when STOP mode is released does not include the time after STOP
mode release until clock oscillation starts (“a” below) regardless of whether
STOP mode is released by RESET input or interrupt generation.
STOP mode release
X1 pin voltage
waveform
a
Remarks 1.
Values in parentheses are reference values for operation with f
XP
= 10 MHz.
2.
f
XP
: X1 input clock oscillation frequency