CHAPTER 1 OUTLINE
User’s Manual U16228EJ2V0UD
34
1.7 Outline of Functions
(1/2)
Item
μ
PD780131
μ
PD780132
μ
PD780133
μ
PD780134
μ
PD78F0134
μ
PD780136
μ
PD780138
μ
PD78F0138
Mask ROM
8 K
16 K
24 K
32 K
48 K
60 K
Flash memory
32 K
Note
60 K
Note
High-speed RAM
512
1 K
1 K
Note
1 K
1 K
Note
Internal
memory
(bytes)
Expansion RAM
1 K
1 K
Note
Memory space
64 KB
X1 input clock (oscillation
frequency)
Ceramic/crystal/external clock oscillation
Standard products,
(A) grade products
REGC pin is connected directly to V
DD
:
10 MHz (V
DD
= 4.0 to 5.5 V), 8.38 MHz (V
DD
= 3.3
to 5.5 V), 5 MHz (V
DD
= 2.7 to 5.5 V)
1
μ
F capacitor is connected to REGC pin: 8.38 MHz (V
DD
= 4.0 to 5.5 V)
(A1) grade products
REGC pin is connected directly to V
DD
:
10 MHz (V
DD
= 4.0 to 5.5 V), 8.38 MHz (V
DD
= 4.0
to 5.5 V), 5 MHz (V
DD
= 3.3 to 5.5 V)
(A2) grade products
REGC pin is connected directly to V
DD
:
8.38 MHz (V
DD
= 4.0 to 5.5 V), 5 MHz (V
DD
= 3.3
to 5.5 V)
Ring-OSC clock
(oscillation frequency)
On-chip Ring oscillation (240 kHz (TYP.))
Subsystem clock
(oscillation frequency)
Crystal/external clock oscillation (32.768 kHz)
General-purpose registers
8 bits
×
32 registers (8 bits
×
8 registers
×
4 banks)
0.2
μ
s/0.4
μ
s/0.8
μ
s/1.6
μ
s/3.2
μ
s (X1 input clock: @ f
XP
= 10 MHz operation)
8.3
μ
s/16.6
μ
s/33.2
μ
s/66.4
μ
s/132.8
μ
s (TYP.) (Ring-OSC clock: @ f
R
= 240 kHz (TYP.)
operation)
Minimum instruction execution
time
122
μ
s (subsystem clock: when operating at f
XT
= 32.768 kHz)
Instruction set
16-bit operation
Multiply/divide (8 bits
×
8 bits, 16 bits
÷
8 bits)
Bit manipulate (set, reset, test, and Boolean operation) BCD adjust, etc.
I/O ports
Total:
51
CMOS I/O
CMOS input
CMOS output
N-ch open-drain I/O
38
8
1
4
Timers
16-bit timer/event counter: 2 channels (1 channel only in the
μ
PD780131, 780132)
8-bit timer/event counter: 2 channels
8-bit timer:
2 channels
Watch timer
1 channel
Watchdog timer:
1 channel
Timer outputs
5 (PWM output: 3)
6 (PWM output: 3)
Clock output
78.125 kHz, 156.25 kHz, 312.5 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(X1 input clock: 10 MHz)
32.768 kHz (subsystem clock: 32.768 kHz)
Buzzer output
1.22 kHz, 2.44 kHz, 4.88 kHz, 9.77 kHz (X1 input clock: 10 MHz)
A/D converter
10-bit resolution
×
8 channels
Note
The internal flash memory capacity, internal high-speed RAM capacity, and internal expansion RAM capacity
can be changed using the internal memory size switching register (IMS) and the internal expansion RAM size
switching register (IXS).