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CHAPTER 3 CPU ARCHITECTURE
User
’
s Manual U15017EJ2V0UD
3.2 Internal ROM Area
The following products in the
μ
PD784976A Subseries have internal ROMs that can store the programs and table
data.
If the internal ROM area or internal data area overlap when the LOCATION 0H instruction is executing, the internal
data area becomes the access target. The internal ROM area in the overlapping part cannot be accessed.
Part Number
Internal ROM
Address Area
LOCATION 0H Instruction
LOCATION 0FH Instruction
μ
PD784975A
96 K
×
8 bits
(Mask ROM)
00000H to 0E9FFH
10000H to 17FFFH
00000H to 17FFFH
μ
PD78F4976A
128 K
×
8 bits
(Flash memory)
00000H to 0E9FFH
10000H to 1FFFFH
00000H to 1FFFFH
The internal ROM can be accessed at high speed. Usually, a fetch is at the same speed as an external ROM fetch.
By setting (to 1) the IFCH bit of the memory expansion mode register (MM), the high-speed fetch function is used.
An internal ROM fetch is a high-speed fetch (fetch in two system clocks in 2-byte units).
If the instruction execution cycle similar to the external ROM fetch is selected, waits are inserted by the wait function.
However, when a high-speed fetch is used, waits cannot be inserted for the internal ROM. However, do not set external
waits for the internal ROM area. If an external wait is set for the internal ROM area, the CPU enters the deadlock
state. The deadlock state is only released by a reset input.
RESET input causes an instruction execution cycle similar to the external ROM fetch cycle.