參數資料
| 型號： | PCX7447AVGH1167NB |
| 廠商： | Atmel |
| 文件頁數： | 49/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT 1167MHZ 360CBGA |
| 標準包裝： | 44 |
| 處理器類型： | PowerPC 32-位 RISC |
| 速度： | 1.167GHZ |
| 電壓： | 1.1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 360-CBBGA 裸露焊盤 |
| 供應商設備封裝： | 360-CBGA（25x25） |
| 包裝： | 托盤 |
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6
0833E–HIREL–01/07
PC7447A
e2v semiconductors SAS 2007
– Address translation for 4-Kbyte pages, variable-sized blocks, and 256-Mbyte segments
– Memory programmable as write-back/write-through, caching-inhibited/caching-allowed, and
memory coherency enforced/memory coherency not enforced on a page or block basis
– Separate IBATs and DBATs (eight each) also defined as SPRs
– Separate instruction and data translation look aside buffers (TLBs)
Both TLBs are 128-entry, two-way set-associative, and use a LRU replacement algorithm
TLBs are hardware- or software-reloadable (that is, a page table search is performed in
hardware or by system software on a TLB miss).
Efficient data flow
– Although the VR/LSU interface is 128 bits, the L1/L2 bus interface allows up to 256 bits
– The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the VRs
– L2 cache is fully pipelined to provide 256 bits per processor clock cycle to the L1 cache
– As many as eight outstanding, out-of-order, cache misses are allowed between the L1 data
cache and the L2 bus
– As many as 16 out-of-order transactions can be present on the MPX bus
– Store merging for multiple store misses to the same line. Only coherency action taken
(address-only) for store misses merged to all 32 bytes of a cache block (no data tenure
needed)
– Three-entry finished store queue and five-entry completed store queue between the LSU
and the L1 data cache
– Separate additional queues for efficient buffering of outbound data (such as castouts and
write-through stores) from the L1 data cache and L2 cache
Multiprocessing support features include the following:
– Hardware-enforced, MESI cache coherency protocols for data cache
– Load/store with reservation instruction pair for atomic memory references, semaphores, and
other multiprocessor operations
Power and thermal management
– A new dynamic frequency switching (DFS) feature allows the processor core frequency to be
halved through software to reduce power consumption
– The following three power-saving modes are available to the system:
Nap: Instruction fetching is halted. Only the clocks for the time base, decrementer, and JTAG
logic remain running. The part goes into the doze state to snoop memory operations on the
bus and then back to nap using a QREQ/QACK processor-system handshake protocol.
Sleep: Power consumption is further reduced by disabling bus snooping, leaving only the
PLL in a locked and running state. All internal functional units are disabled.
Deep sleep: When the part is in the deep Sleep state, the system can disable the PLL. The
system can then disable the SYSCLK source for greater system power savings. Power-on
reset procedures for restarting and relocking the PLL must be followed upon exiting the deep
sleep state.
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相關代理商/技術參數 |
參數描述 |
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| PCX7448MGH1000NC | 制造商:e2v technologies 功能描述:MPU RISC 32BIT 0.09UM 1GHZ 1.5V/1.8V/2.5V 360HITCE CBGA - Trays |
| PCX7448MGH1250NC | 制造商:e2v technologies 功能描述:PCX7448MGH1250NC - Trays |
| PCX7448VGH1000NC | 制造商:e2v technologies 功能描述:PCX7448VGH1000NC - Trays |
| PCX7448VGH1250NC | 制造商:e2v technologies 功能描述:MPU RISC 32BIT 0.09UM 1.25GHZ 1.5V/1.8V/2.5V 360HITCE CBGA - Trays |
| PCX7457VGH1000NC | 功能描述:IC MPU 32BIT 1000MHZ 483CBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標準包裝:60 系列:SCC 處理器類型:Z380 特點:全靜電 Z380 CPU 速度:20MHz 電壓:5V 安裝類型:表面貼裝 封裝/外殼:144-LQFP 供應商設備封裝:144-LQFP 包裝:托盤 |
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