參數(shù)資料
型號: PCM1606E
英文描述: 24-BIT, 192-kHz SAMPLING, 6-CHANNEL, ENHANCED MULTILEVEL, DELTA-SIGMA DIGITAL-TO-ANALOG CONVERTER
中文描述: 24位192 kHz的采樣,6通道,加強多層次,Δ-Σ數(shù)字到模擬轉(zhuǎn)換器
文件頁數(shù): 23/27頁
文件大?。?/td> 385K
代理商: PCM1606E
PCM1606
SLES014B – OCTOBER 2001 – REVISED AUGUST 2002
5
www.ti.com
electrical characteristics, all specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz,
system clock = 384 fS and 24-bit data (unless otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
PCM1606E
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL FILTER PERFORMANCE
FILTER CHARACTERISTICS
Passband
±0.03 dB
0.454 fS
Passband
–3 dB
0.487 fS
Stopband
0.546 fS
Passband ripple
±0.03
dB
Stopband attenuation
Stopband = 0.546 fS
–50
dB
Stopband attenuation
Stopband = 0.567 fS
–55
dB
ANALOG FILTER PERFORMANCE
Frequency response
At 20 kHz
–0.03
dB
POWER SUPPLY REQUIREMENTS (see Note 4)
VCC
Voltage range
4.5
5
5.5
VDC
fS = 44.1 kHz/384 fS
50
65
ICC
Supply current
fS = 96 kHz/256 fS
72
mA
ICC
Su
ly current
fS = 192 kHz/128 fS
68
mA
fS = 44.1 kHz/384 fS
250
358
Power dissipation
fS = 96 kHz/256 fS
360
mW
Power dissi ation
fS = 192 kHz/128 fS
340
mW
TEMPERATURE RANGE
Operation temperature
–25
85
°C
θJA
Thermal resistance
20-pin SSOP
115
°C/W
NOTES:
3. Analog performance specs are tested using System Two Cascade Plus by Audio Precision with 400-Hz HPF, 30-kHz LPF on at RMS
with 20-kHz LPF, 400-Hz HPF in calculation.
Shibasoku #725 THD meter, 400 Hz HPF, 30 kHz LPF on, at average mode with 20-kHz bandwidth limiting. The load connected
to the analog output is 5 k
or larger via capacitance coupling.
4. Condition in 192-kHz operation is channel 3 through channel 6 are disabled.
timing requirements
system clock input
The PCM1606 requires a system clock for operating the digital interpolation filters and multilevel delta-sigma
modulators. The system clock is applied at the SCKI (pin 20). Table 1 shows examples of system clock
frequencies for common audio sampling rates.
Figure 1 shows the timing requirements for the system clock input. For optimal performance, it is important to
use a clock source with low phase jitter and noise. Texas Instruments’ PLL1700 multiclock generator is an
excellent choice for providing the PCM1606 system clock source.
The 192-kHz sampling frequency operation is available on DATA1 for VOUT1 and VOUT2. When the system clock
of 128 fS or 192 fS is detected, VOUT3, VOUT4, VOUT5 and VOUT6 are automatically forced to the bipolar zero
level (= 0.5 VCC). Table 1 lists the typical system clock frequency.
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