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參數(shù)資料
| 型號： | PCM1604 |
| 英文描述： | 24-Bit, 192kHz Sampling,6-Channel, Enhanced Multi-Level, Delta-Sigma DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 24位192kHz采樣,6 -通道，增強(qiáng)的多級，Δ-Σ數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 16/32頁 |
| 文件大?。?/td> | 263K |
| 代理商： | PCM1604 |
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16
PCM1604, PCM1605
last 8 bits of the 16-bit read cycle, which corresponds to the
8 data bits of the register indexed by the REG[6:0] bits of
Control Register 11. The Read cycle is completed when ML
is set to ‘1’, immediately after the MC clock cycle for the
least significant bit of indexed control register has com-
pleted.
AUTO-INCREMENT READ OPERATION
The Auto-Increment Read function allows for multiple reg-
isters to be read sequentially. The Auto-Increment Read
function is enabled by setting the INC bit of Control Register
11 to ‘1’. The sequence always starts with Register 1, and
ends with the register indexed by the REG[6:0] bits in
Control Register 11.
Figure 9 shows the timing for the Auto-Increment Read
operation. The operation begins by writing Control Register
11, setting INC to ‘1’ and setting REG[6:0] to the last
register to be read in the sequence. The actual Read opera-
50% of V
DD
50% of V
DD
50% of V
DD
50% of V
DD
ML
MC
MDI
MDO
t
MLS
t
MCH
t
MCY
t
MOS
t
MDS
t
MCH
t
MCL
t
MHH
t
MLH
LSB
LSB
tion starts on the next HIGH to LOW transition of the ML
pin. The Read cycle starts by setting the R/W bit of the
control word to ‘1’, and setting all of the IDX[6:0] bits to
‘0.’. All subsequent bits input on the MDI are ignored while
ML is set to ‘0.’ For the first 8 clocks of the Read cycle,
MDO is set to a high-impedance state. This is followed by
a sequence of 8-bit words, each corresponding to the data
contained in Control Registers 1 through N, where N is
defined by the REG[6:0] bits in Control Register 11. The
Read cycle is completed when ML is set to ‘1’, immediately
after the MC clock cycle for the least significant bit of
Control Register N has completed.
CONTROL INTERFACE TIMING REQUIREMENTS
Figure 10 shows a detailed timing diagram for the Serial
Control interface. Pay special attention to the setup and hold
times, as well as t
MLS
and t
MLH
, which define minimum delays
between edges of the ML and MC clocks. These timing
parameters are critical for proper control port operation.
SYMBOL
PARAMETER
MIN
MAX
UNITS
t
MCY
t
MCL
t
MCH
t
MHH
t
MLS
t
MLH
t
MDI
t
MDS
t
MOS
MC Pulse Cycle Time
MC Low Level Time
MC High Level Time
ML High Level Time
ML Falling Edge to MC Rising Edge
ML Hold Time
(1)
Hold Time
MDL Set Up Time
MC Falling Edge to MDSO Stable
100
50
50
300
20
20
15
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
NOTE: (1) MC rising edge for LSB to ML rising edge.
FIGURE 10. Control Interface Timing.
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