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| 型號： | PCF51JM64VLH |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 21/49頁 |
| 文件大?。?/td> | 0K |
| 描述： | MCU 32BIT 64K FLASH 64-LQFP |
| 標準包裝： | 160 |
| 系列： | MCF51JM |
| 核心處理器： | Coldfire V1 |
| 芯體尺寸： | 32-位 |
| 速度： | 50MHz |
| 連通性： | CAN，I²C，SCI，SPI，USB OTG |
| 外圍設(shè)備： | LVD，PWM，WDT |
| 輸入/輸出數(shù)： | 51 |
| 程序存儲器容量： | 64KB（64K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 16K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 12x12b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 64-LQFP |
| 包裝： | 托盤 |
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MCF51JM128 ColdFire Microcontroller, Rev. 4
Preliminary Electrical Characteristics
Freescale Semiconductor
28
2.11
AC Characteristics
This section describes ac timing characteristics for each peripheral system.
2.11.1
Control Timing
5 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
BUS.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for
a given interval.
6 625 ns represents 5 time quanta for CAN applications, under worst case conditions of 8 MHz CAN bus clock, 1 Mbps CAN
bus speed, and 8 time quanta per bit for bit time settings. 5 time quanta is the minimum time between a synchronization edge
and the sample point of a bit using 8 time quanta per bit.
7 Below D
lock minimum, the MCG is guaranteed to enter lock. Above Dlock maximum, the MCG will not enter lock. But if the
MCG is already in lock, then the MCG may stay in lock.
8 Below D
unl minimum, the MCG will not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock.
Table 17. Control Timing
Num
C
Parameter
Symbol
Min
Typ1
1 Typical values are based on characterization data at V
DD = 5.0V, 25C unless otherwise stated.
Max
Unit
1
Bus frequency (tcyc = 1/fBus)fBus
dc
—
24
MHz
2
Internal low-power oscillator period
tLPO
700
1300
s
External reset pulse width2
(tcyc = 1/fSelf_reset)
2 This is the shortest pulse guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to override
reset requests from internal sources.
textrst
100
—
ns
4
Reset low drive
trstdrv
66 x tcyc
—ns
5
Active background debug mode latch setup time
tMSSU
500
—
ns
6
Active background debug mode latch hold time
tMSH
100
—
ns
7
IRQ pulse width
Asynchronous path2
Synchronous path3
3 This is the minimum pulse width guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not
be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
tILIH, tIHIL
100
1.5 x tcyc
——
ns
8
KBIPx pulse width
Asynchronous path2
Synchronous path3
tILIH, tIHIL
100
1.5 x tcyc
——
ns
9
Port rise and fall time (load = 50 pF)4
Slew rate control disabled (PTxSE = 0) High drive
Slew rate control enabled (PTxSE = 1) High drive
Slew rate control disabled (PTxSE = 0) Low drive
Slew rate control enabled (PTxSE = 1) Low drive
4 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40C to 105C.
tRise, tFall
—
11
35
40
75
ns
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