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參數(shù)資料
| 型號(hào)： | PCF2113X |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | LCD controllers/drivers |
| 中文描述： | LCD控制器/驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 32/72頁 |
| 文件大?。?/td> | 332K |
| 代理商： | PCF2113X |
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2001 Dec 19
32
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2113x
10 INTERFACES TO MICROCONTROLLER
10.1
Parallel interface
ThePCF2113xcansenddataineithertwo4-bitoperations
or one 8-bit operation and can thus interface to 4-bit or
8-bit microcontrollers.
In 8-bit mode data is transferred as 8-bit bytes using the
8 data lines DB7 to DB0. Three further control lines E,
RS and R/W are required (see Chapter 6).
In 4-bit mode data is transferred in two cycles of 4 bits
each using pins DB7 to DB4 for the transaction.
The higher order bits (corresponding to DB7 to DB4 in
8-bit mode) are sent in the first cycle and the lower order
bits (DB3 to DB0 in 8-bit mode) in the second cycle. Data
transfer is complete after two 4-bit data transfers. It should
be noted that two cycles are also required for the busy flag
check. 4-bit operation is selected by instruction, see
Figs 17 to 19 for examples of bus protocol.
In 4-bit mode, pins DB3 to DB0 must be left open-circuit.
They are pulled up to V
DD
internally.
10.2
I
2
C-bus interface
The I
2
C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are the
Serial Data line (SDA) and the Serial Clock Line (SCL).
Both lines must be connected to a positive supply via
pull-up resistors. Data transfer may be initiated only when
the bus is not busy.
Each byte of eight bits is followed by an acknowledge bit.
The acknowledge bit is a HIGH level signal put on the bus
by the transmitter during which time the master generates
anextraacknowledgerelatedclockpulse.Aslavereceiver
which is addressed must generate an acknowledge after
the reception of each byte.
Also a master receiver must generate an acknowledge
after the reception of each byte that has been clocked out
of the slave transmitter.
The device that acknowledges must pull-down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration).
MGA804
RS
E
DB7
R/W
DB6
DB5
DB4
instruction
write
busy flag and
address counter read
data register
read
IR7
IR3
BF
AC3
DR7
DR3
IR6
IR2
AC6
AC2
DR6
DR2
IR5
IR1
AC5
AC1
DR5
DR1
IR4
IR0
AC4
AC0
DR4
DR0
Fig.17 4-bit transfer example.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCF2113DHF4 | LCD controllers/drivers |
| PCF2113WU2 | LCD controllers/drivers |
| PCF2113F2 | LCD controller/driver(LCD控制器/驅(qū)動(dòng)器) |
| PCF211310 | LCD controller/driver(LCD控制器/驅(qū)動(dòng)器) |
| PCF21132 | LCD controller/driver(LCD控制器/驅(qū)動(dòng)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCF2114AH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver |
| PCF2114AU | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver |
| PCF2114AU/10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:LCD controller/drivers |
| PCF2114AU/12 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:LCD controller/drivers |
| PCF2114CH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver |
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