參數(shù)資料
型號(hào): PCF2113E
廠商: NXP Semiconductors N.V.
英文描述: LCD controller/driver
中文描述: LCD控制器/驅(qū)動(dòng)器
文件頁(yè)數(shù): 41/72頁(yè)
文件大小: 332K
代理商: PCF2113E
2001 Dec 19
41
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2113x
14 AC CHARACTERISTICS
V
DD1
= 1.8 to 5.5 V; V
DD2
= V
DD3
= 2.2 to 4.0 V; V
SS
= 0 V; V
LCD
= 2.2 to 6.5 V; T
amb
=
40 to +85
°
C; unless otherwise
specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
f
FR
f
osc
f
OSC(ext)
t
osc(st)
t
W(PD)
t
SW(PD)
Timing characteristics of parallel interface;
note 2
LCD frame frequency (internal clock)
oscillator frequency (not available at any pin)
external clock frequency
oscillator start-up time after power-down
power-down HIGH-level pulse width
tolerable spike width on PD pin
V
DD
= 5.0 V
45
140
140
1
95
250
200
147
450
450
300
90
Hz
kHz
kHz
μ
s
μ
s
ns
note 1
note 1
W
RITE OPERATION
(
WRITING DATA FROM MICROCONTROLLER TO
PCF2113
X
); see Fig.27
T
cy(en)
t
W(en)
t
su(A)
t
h(A)
t
su(D)
t
h(D)
R
EAD OPERATION
(
READING DATA FROM
PCF2113
X TO MICROCONTROLLER
); see Fig.28
enable cycle time
enable pulse width
address set-up time
address hold time
data set-up time
data hold time
500
220
50
25
60
25
ns
ns
ns
ns
ns
ns
T
cy(en)
t
W(en)
t
su(A)
t
h(A)
t
d(D)
enable cycle time
enable pulse width
address set-up time
address hold time
data delay time
500
220
50
25
5
150
250
100
ns
ns
ns
ns
ns
ns
ns
V
DD1
> 2.2 V
V
DD1
> 1.5 V
t
h(D)
data hold time
Timing characteristics of I
2
C-bus interface;
see Fig.29; note 2
f
SCL
t
LOW
t
HIGH
t
SU;DAT
t
HD;DAT
t
r
t
f
C
b
t
SU;STA
t
HD;STA
SCL clock frequency
SCL clock LOW period
SCL clock HIGH period
data set-up time
data hold time
SCL and SDA rise time
SCL and SDA fall time
capacitive bus line load
set-up time for a repeated START condition
START condition hold time
1.3
0.6
100
0
15 + 0.1 C
b
15 + 0.1 C
b
0.6
0.6
400
300
300
400
kHz
μ
s
μ
s
ns
ns
ns
ns
pF
μ
s
μ
s
note 1 and 3
note 1 and 3
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